dither problem on fractional spur in PLL

[fenfei]

Hello Everyone;
I have designed a PLL using ADF4156,a fractional N PLL.Output frequency is 1300MHz~1600MHz,PFD frequency is 30MHz,frequency step is 10kHz,loop width is 50kHz.
I found that in low noise mode, MOD=2999,there is fractional spur at 10kHz,20kHz,30kHz,.. offset with a level of about -47dBc. So, I set the PLL in low spur mode which means the dither is turned on.But in low spur mode ,the phase noise raised about 10 dB,while the spurs are still -47dBc! It looks like the dither has no impact on these fractional spur,why?
I changed the frequency step to 100kHz,So the spur appeared at 100kHz,200kHz...offset.
I changed the PFD frequency to 10MHz ,the spurs are not changed.
I changed the MOD from 2999 to 3000,I found the spur varied with FRAC.when FRAC is 1000 and 2000, there is a large spur appearing at ±5kHz offset (-35dBc).
all above trying are in low spur mode.
Is there anyone meet the similar problem?

 

[fenfei]

can anyone help me?

 

[biff44]

Yep, fractional PLLs stink for spurs! It all comes under the law "there is no such thing as a free lunch".

I am not familiar with the dither function on that chip, but I suspect it is cleaning up other spurs. You just have a virtual comparison frequency spur that is much closer to the carrier than you would have thought, because of the fractionality. I don't think there is any way to get rid of it, other than carefully choosing the math so those fractions don't show up, or using dual plls, etc.

 

[fenfei]

the ADF4156 datasheet said that if dither is turned on,then the fractional spurs will act like random noise .there will only be integer boundary spurs(IBS).

But I don't think the spur is IBS,because they vary with the freq step.

Can anyone explain the IBS?