# Display DDR SDRAM data on LEDs (XUPV2P)

Status
Not open for further replies.

#### BlackOps

##### Full Member level 5
ddr leds

At this stage now, i am currently writing/reading from DDR SDRAM.

i have also added own peripheral for LEDs. This peripheral will take one byte of data from DDR SDRAM. and based on its value will turn specific LEDs ON or OFF.

i was referencing to your example of Adding VHDL design to Peripheral, from ur website. about multiplier...

ur multiplier takes 2 values multiplies them, and stores result in readFIFO.

but my peripheral, will take value from DDR, compare it, then turn ON specific LED. (before i succeeded in just writing data to DDR and reading it to UART)

i have organized everything, but at last stage, when i generate bitstream... i get errors:

Code:
ERROR:NgdBuild:755 - "system.ucf" Line 302: Could not find net(s) 'LED_0' in the
design.  To suppress this error specify the correct net name or remove the
constraint.  The 'Allow Unmatched LOC Constraints' ISE property can also be
set ( -aul switch for command line users).
ERROR:NgdBuild:755 - "system.ucf" Line 303: Could not find net(s) 'LED_1' in the
design.  To suppress this error specify the correct net name or remove the
constraint.  The 'Allow Unmatched LOC Constraints' ISE property can also be
set ( -aul switch for command line users).
ERROR:NgdBuild:755 - "system.ucf" Line 304: Could not find net(s) 'LED_2' in the
design.  To suppress this error specify the correct net name or remove the
constraint.  The 'Allow Unmatched LOC Constraints' ISE property can also be
set ( -aul switch for command line users).
ERROR:NgdBuild:755 - "system.ucf" Line 305: Could not find net(s) 'LED_3' in the
design.  To suppress this error specify the correct net name or remove the
constraint.  The 'Allow Unmatched LOC Constraints' ISE property can also be
set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "system.ucf".

i have added the following inthe user_logic.vhd of my peripheral:

Code:
    -- ADD USER PORTS BELOW THIS LINE ------------------
LED_0: out std_logic;
LED_1: out std_logic;
LED_2: out std_logic;
LED_3: out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------

and then mapped those ports like this:

Code:
  --USER logic implementation added here
leddata_0: leddata
port map (
Clk  =>  Bus2IP_Clk,
a  =>  WFIFO2IP_Data(0 to 7),
led0 =>  LED_0,
led1 =>  LED_1,
led2 =>  LED_2,
led3 =>  LED_3);

do you have idea how to get rid of this error? any advice?

or maybe i should use readFIFO for mapping it onto the LED_xx ?

do u think it is a good idea to write data from controller to the peripheral hardware through readFIFO?

thanks!

#### firefoxPL

##### Member level 1
edk implementation of ddr sdram

it's been some time since I tried to put my logic into EDK so I don't remember what needed to be done to accomplish it, but I used this tutorial from Xilinx it should help

### BlackOps

Points: 2

#### firefoxPL

##### Member level 1
xupv2p tutorial

I think that basically you need to manualy update your ucf file and add there the appropriate nets

### BlackOps

Points: 2

#### BlackOps

##### Full Member level 5
data on leds

well, problem is, that i DID update my UCF and ADDED manually my nets... it stil gives these errors....

any idea?

Firefox, thank u for help, i didnt fix problem yet, but ur papers are helpful! now, could u please post here the LAB1 and LAB2? and other LABs? thanks in advance!

#### firefoxPL

##### Member level 1
xupv2p leds

this lab I just found on google, but you can get the whole course just by registering on **broken link removed**, of course it's free

#### RDRyan

##### Full Member level 2
Maybe you should define another 4 signals LED_0,LED_1,LED_2,LED_3 like this:
signal LED_0:std_logic;
signal LED_1:std_logic;
signal LED_2:std_logic;
signal LED_3:std_logic;
then use these 4 signals to do port map.

Ryan

#### vlsi_whiz

##### Full Member level 4
This error is generated during the PAR stage. The main cause is coz u havent declared these LED signals as external connections in the Microblaze system. To do this...after you've added your custom logic... click the (+) sign under your IP module and connect the PLB / OPB bus to one port of your logic. Next, switch to the PORTS tab in EDK and click the (+) sign next to your IP logic and expand it. Here you will find the connections, net names for your logic core. Make sure you select each NET you want to connect to external LED and select Make External connection from the drop-down list.

When you do this..EDK will automatically assign a net name for your signal. Now... update the net name in the UCF file using these net names. Then recompile..this should solve the problem.

Status
Not open for further replies.