discrete multi-stage vhf small signal amplifier

[cgchas]

I am designing a wide band amplifier (20Hz to 50MHz) that follows a frequency compensated attenuator network. This amplifier will provide signal to a frequency counter that I have built.

The amplifier is expected function with signals as small as 15mVpp - 50mVpp input, but for breadboard testing, I have been bypassing the attenuator and just using a small protection network (270p cap in series with 100 ohm resistor both in parallel to 178k resistor followed by a diode AC clamp). A 3.3 volt 50MHz input comes through the diodes at about just under 500mVpp.

The first amplification stage is a buffer/impedance converter, common drain BF256B N-Channel JFET direct coupled to a common collector 2N3906 PNP BJT . This transforms impedance from high (>1Mohm) down to about 150 ohms and then from 150 down to 50 (I think). The voltage out of this buffer is about 1Vpp and if I load test it with a 50-ohm resistor it drops to 500mVpp.

From there I have tried quite a few different things. What I want to do, is from a +10V single supply amplify 15mVpp up high enough so that the final current buffer stage can drive a 5V 50-ohm load to 74F Schottky NAND gates. This output voltage does not technically need to be 5 volts. It can be lower as far as the NAND gates are concerned (they technically work at 2V input), but I would like to know how to get as close to 10 as possible from a 10 volt rail. I am not opposed to line drivers but I still want to know how to make this signal with transistors if it is possible. I am not opposed to resorting to a higher supply rail if it is absolutely necessary, but so far I do not know if it is.

Here is what I have tried so far..
BC547C common emitter capacitively coupled to 2N3904 common collector. From just this pair I can get from 1V to 2.5-2.75Vpp. With 2 additional stages I can only get to about 4.5Vpp. I cannot seem to get around the loading effects of each stage using the basic CE / CC combination regardless of how I bias them.

If I bootstrap the follower buffers instead of the basic emitter followers this definitely lowers output impedance, but my lack of experience with these is making it difficult to bias them for proper output impedance. All of my tests have shown their output resistances to be <3-4 ohms, but I have to admit, they do seem to buffer very well. With a single BC547C and 2N3904 I can get to just over 4.5Vpp but not at 50-ohms output. I have not yet been able to mathematically process the AC equivalent model of the bootstrap (positive feedback) follower yet and I would like to correctly get to 50 ohms. I'd love some guidance with this, but only if this is the recommended way to solve my problem.

I have tried 4 capacitively coupled stages of BC547C common emitters followed by a single 2N3904 buffer. The best I have been able to get from this is just over 4Vpp.

I have also tried a OPA830 Op-Amp. I have tried it right after the first N-JFET/PNP stage as well as I have tried it after one or more stages of the BC547C/2N3904 combinations. The best I have been able to come up with (with reasonable stability) is 5.5 - 6Vpp. (7-8 volts with jitter and some instability). I am not opposed to using 1 or more op amps in my final design but I would very much like to know how to do this with basic discrete models.

Here are the top 2 questions I have after experimenting for the past 3 weeks with this project. I have more but this post is already getting lengthy

1) Is an arrangement of reasonably basic discrete amplifier models, one or more stages, that gets voltage up to 8-9 volts from a 10 volt rail possible to 50MHz?

By basic, I mean voltage divider biased BJT and self-biased JFET or directly coupled common emitter (or source) with emitter or (source) followers.

2) For a multiple stage high frequency small signal amplifier, do I need to be matching output to input impedance at each stage or should I be just worried about not loading subsequent stages by making input impedances as high as possible? In other words, are signal reflections an issue at these levels?

My main criteria here is getting as close to 10V from 15mV as possible and the best I achieved so far is 6V from 500mV and that is without going through the attenuator, so there is plenty of room for improvement.

Any comments or suggestions are appreciated.

 

[FvM]

May I ask you to sketch a schematic of the circuit you are describing verbosely?

 

[cgchas]

Sure thing.
For reference I attached what I am using for input and initial current amplification. The attenuator is removed since I am not actually testing with it yet. There have been many iterations of attempts to amplify voltage towards the rail voltage using basic configurations of transistors. I'd be interested in knowing what expectations I should be having with the 10 volt rail at 50MHz. It's just not something I am seeing in any of my books or online outside of op-amps.

 

[FvM]

It's basically a dual follower with gain < 1. I'm not sure if this is what you want.

It should have a high ohmic bias resistor parallel to D1/D2.

 

[cgchas]

It's basically a dual follower with gain < 1. I'm not sure if this is what you want.

It should have a high ohmic bias resistor parallel to D1/D2.

I believe this is what I want up to this point. It is what comes after that I am asking for suggestions.
I did try a 1Mohm gate resistor and there was no noticeable difference in output. The test I used to check output was placing a 50-ohm load resistor at the second follower's emitter output which dropped the signal by about 50% which leads me to believe that the output of the 2nd follower is about 50-ohms impedance.

My question basically is what transistor-based approach would be most effective after the second follower to obtain the highest voltage gain possible from the 10V rail at 50MHz?

 

[cgchas]

what transistor-based approach would be most effective after the second follower to obtain the highest voltage gain possible from the 10V rail at 50MHz?

Ok so I realize now my gain calculations have been off because I have been attempting to amplify towards 10Vpp output off a 10V rail and that this is not small-signal model anymore, but rather this is non-linear/large-signal which means output is limited by the power supply voltage. If I am correct, what I am actually looking for is topology and formula for large-signal amplification. Is 7.5Vpp output reasonable using transistors with Vcc=10V ?

 

[FvM]

In the present cicruit, the output is limited to about 1 Vpp by the input clamp diodes and gain < 1. The load impedance must be considered, too.

 

[cgchas]

In the present cicruit, the output is limited to about 1 Vpp by the input clamp diodes and gain < 1. The load impedance must be considered, too.

Yes, the present circuit that I posted is the initial buffer. Gain is less than one and impedance is converted from high to low. It is converted to low in order to drive a voltage amplifier which is what I am asking about.

What voltage amplifier topology is recommended for high frequency large-signal amplification?

 

[FvM]

drive a voltage amplifier which is what I am asking about

I presumed you'd show the schematic of the amplifier you are asking about.

 

[cgchas]

I presumed you'd show the schematic of the amplifier you are asking about.

I apologize for my miscommunication. The amplifier I am asking about is one that I wish to design for large signal voltage gain. Everything I have tried so far has been under the assumption that gain would be relatively constant and that the transistors would be operating in their linear region. I believe that this assumption was not valid because I want to amplify volts, not millivolts, with regards to a 10V supply.

For the sake of providing at least something that I have tried that has not worked, I will post the basic model used and list one set of values that I tried:

https://commons.wikimedia.org/wiki/File:Common_emitter.png

Vcc = 10V
Beta = 420
Rc = 340 ohms
R1 = 22k ohms
R2 = 2.2k ohms
Re = 10 ohms (with a trimmer all values tried from 1 to 100 ohms)
Cin and Cout = .01uF
Cbypass = .01uF

Using the described model with the listed values repeated over many cascaded stages (5 or 6), gain per stage seems to fall off drastically above 1.5V - 2V.

I have been working on calculations for collector-feedback common emitter for better control over linear operation, but again, I think what I am seeking to do is non-linear and requires a topology or model that considers the limitation of the supply voltage on the final output voltage. For this, I do not have a schematic as I am asking for help with creating one.