PityOnU
Newbie level 2
I am having issues pushing a rather large design of mine through Design Compiler. It keeps OPT-1206 and OPT-1207'ing away all of my registers ("------ is a constant and will be removed.")
I have tried the following commands:
set_dont_touch <entity name>
set compile_delete_unloaded_sequential_cells false
set hdlin_preserve_sequential true
But still the thing is wiping out a ton of my gates and making the design not work correctly in simulation. Does anyone know how I would disable all of these optimizations?
I have tried the following commands:
set_dont_touch <entity name>
set compile_delete_unloaded_sequential_cells false
set hdlin_preserve_sequential true
But still the thing is wiping out a ton of my gates and making the design not work correctly in simulation. Does anyone know how I would disable all of these optimizations?