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[Dis] How to quickly verify data intensive RTL by using SVA?

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bigrice911

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I want to verify a simple DSP RTL codes, can anybody suggest a good way by using sva?

here is example:
module test_assertion(
data1,
data2,

sum
);
input [11:0] data1;
input [11:0] data2;

output [ 5:0] sum;

logic [12:0] d1;
logic [11:0] d2;
logic [14:0] d3;
logic [ 5: 0] d4;

//RTL model
wire [12:0] data_w1 = {data1[11], data1} - {data2[11], data2}; //signed minor
wire [11:0] data_w2 = data_w1[12] ? (~data_w1[11:0] + 1) : data_w1[11:0]; //abs
wire [14:0] data_w3 = {data_w2, 2'b00} + {1'b0, data_w2,1'b0}; //mutiply six
wire [ 5:0] data_w4 = data_w3[14:6] ? 6'd63 : data_w3[5:0]; //clip to 6-bit

assign sum = data_w4;


//behavior model
always @*
begin
d1 = data1-data2 ;
d2 = d1 ;
d3 = d2*6 ;
d4 = (d3>64)?6'd63:d3[5:0] ;

//assertion

SIGNED_MINOR: assert (data_w1 == d1);
ABS: assert (data_w2 == d2);
MULTIPLY_SIX: assert (data_w3 == d3);
CLIP_TO_SIM: assert (data_w4 == d4);
end
endmodule


I am trying to use sva but simulator tells me the result is incorrect...
I don't how to use this instant assertion.
 

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