Diodes N+: why this N+ diodes is placer inside a P+ ring

[gafsos]

Diodes N+

Hi 2 all,

I need to know why this N+ diodes is placer inside a P+ ring ??

Have u any idea (see picture)

Thanks

 

[fixrouter4400]

Diodes N+

Hi gafsos,

If this is a PMOS with and N+ diodes...then the diode must be placed outside the N ring in order to avoid short connection to the nwell. If this passes LVS then it must be right to place them outside the N+ ring. You can also connect them totally outside the N+ and P+ ring and it'll be the same layout i guess.

Cheers

 

[llbaobao]

Diodes N+

oh,it is often the tricks to add such taps in layout.

If can avoid the short item said by fixrouter4400, the location is not defined.

Though for some case, it is better to put the tap near the gate.

 

[leo_o2]

Diodes N+

P+ ring is a guard ring for hot Nwell?

 

[gafsos]

Re: Diodes N+

leo_o2,

yes it is

Any another suggestions

Thnks

 

[xaxtel]

it is to solve nwell antenna effect. by placing the ndiode, it provide a path for discharge

 

[erikl]

it is to solve nwell antenna effect. by placing the ndiode, it provide a path for discharge

Antenna diodes shouldn't be necessary in this case, as there is already contact to silicon via the drains, which is sufficient.

 

[dick_freebird]

An N+ diode in Psub, is half of a field NMOSFET. The other half
being the nearest other N region. You'd like that FET not to
work. P+ stops the channel.

P+ is also a good local ohmic contact, lowers series resistance
in the diode and lowers base shunt resistance of any parasitic
BJT.

Multiple tie rings are a common latchup protection feature.

Not knowing the process or circuit, conjecture is all we can give.
The real reason is likely some subset.