Diode clamper circuit

[kenambo]

Hi all

I ran the transcient simulation of a clamper circuit which is shown below.

Freq = 60Hz c=14uF R=100K and Diode = 40 nm Deep Nwell diode.

i observed a strange behavior.

the output voltage settles after a particular time period..

and it is clamped too.

But why does this circuit needs a settle time?

Thanks

 

[D.A.(Tony)Stewart]

Consider the charging series resistance* capacitance time constant is multiplied by the duty cycle of the diodes. If forward biased 50% of time, the ESR of diodes and supply is x2 . Diodes have a fairly low but non zero effective series resistance ESR that depends on bulk size of diode and thus voltage rise above saturation and thus current limit.

 

[kenambo]

Hi..

I didnt get you.. as you said, Diode equivalent resistance is the reason for the settling time..

and if i am applying an input means the ESR is equal for the operating frequency . am i right?

and at the starting time, the diode doesn't conduct in reverse bias it starts conduction in reverse bias after some time.

how exactly these changes happening and becomes constant after a particular time. Because my frequency is 60Hz and swing is -10 to 10 V.

Initially my output is -10 to 10 but after a settling time, it changes to 5 to -15V that is clamping as time progress and stay constant at this voltage range.

If you need , i can attach my snaps.

thanks