According to the zilog's design dimmer the decoupling capacitor has a value of 220uF.
We're all tempted to increase this value mainly due to two reasons:
1. To reduce +5v rail ripple
2. To provide the current gate when triac is fired and still keeping a reasonable value for supplying PIC16F628
However, the value of this capacitor can't be increased too much because appears the risk of not being able to charge it quickly after AC voltage zero cross.
When a neutral is used (connection B) you don't encounter this problem because you have this capacitor full charged all the time regardless the triac conduction period.
Your lamp is blinking because:
1. PIC16F628 it's not supplied properly during one half AC cycle when triac should be fire-up (the decoupling capacitor was emptied in the previous AC half cycle and has not reached the appropiate charge value)
2. PIC is supplied but the triac gate current delivered by PIC is not enough to trigger the triac.
The things goes worst when inductive loads are used (like motors or transformers for halogen lams) even if neutral is available.
I can't claim that the bellow recomended steps will cure the problem, but worth to try.
First try to decrease the value of decoupling capacitor down to 100uF and increase the 300nF/250vca up to 470nF/250vca.
You can try to increase the value of 1K resistor which provides the gate current of triac up to a value for which the triac is still able to hold the current requested by the lamp (load).
Look at fig.6 page 4 of Zilog dimmer. The polarity of gate terminal must be referenced to T1 terminal (the gate terminal should be drawed to the T1 terminal side like fig 9 page 7).
If T1 is tied to ground, and pin 14(GND) of Z86E02 is connected as well to N ground acccording to fig.3 page 2, then the triac is fire-up in quadrant I (T2+ G+) and IV (T2- G+) and not II (T2+ G-) and III (T2- G-) as claimed by Zilog's designers.
Just because P20 port source current from VCC and not sink to ground through gate triac.
If the triac must be fired in quadrant II and III, the gate potential must be lower than the potential of T1 terminal.
If GND of Z86E02 is tied to N as T1 terminal, how can P20 output port be negative than GND ?
Looking at the code, there are two macros:
release_ignition where bset p2,.triac_gate P20 goes to 1 logic (source current)
ignite_triac where bclr p2,.triac_gate P20 goes to 0 logic (sink current)
To be honest I don't understand how the circuit is working as long as for fire-up the triac you drive P20 to ground (T1 terminal).
It could work with Z86E02 supplied "bellow N neural" (see bellow) or with two macros function swaped : bclr P2.0 for release_ignition and bset P2.0 for ignite_triac
I suggest to supply your PIC "bellow the N neutral" and I mean with the arm "+" of filter capacitor tied to PIC rail (V+) and obvious connected to N neutral AC line.
and arm "-" of filter capacitor tied to PIC rail (V-). Similar with LS7231 schematic.
This way keep your output port to 1 logic and cleared to 0 when you want triac to be fired. You'll work in quadrant II and III where is suitable.