Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
On my PC i do not have a VHDL compiler to make a small example,
so have you tried the array2d'range or (array2d'right or arry2d'left).
regards
JoseMiguel
IIRC, x'length(2) is defined for this. Most of the dimension attributes are overloaded to default to the first dimension, but do take an argument.
most synthesizers usually list support for arrays of arrays. eg "type mytype is array (natural range <>) of std_logic_vector(7 downto 0)". The tools may not like 2-d arrays in some situations, like unconstrained ports or unconstrained inputs to functions.
There is no overloading of any attributes, the number in brackets refers to the nth dimension (starting from 1, annoyingly) for n-d arrays. But for 1-d array a specific dimension is implied as 1.
You example type is a 1-d array, because it only has 1 range specifier in the array declaration.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
