Digitally controlled delay unit circuit

[blowfish]

Could any one help me in the designing of digital controlled delay unit circuit for my Delay Locked loop Circuit

As i am not able to implement uisng a Verilog Simulation tool ,FPGA ADVANTAGE PRO.
Send me any ALL DIGITAL DELAY LOCKED LOOP CIRCUIT ,as i am not able to find any complete circuit in the internet or books .


Also how to implement "Hiearchial delay unit" (HDU) shown in this paper attached.

 

[blowfish]

Hi,

how to create a dgitally controlled delay unit using a flip flops .Can anyone send me some examples(coding using verilog HDL) or materials or post it in the forum .

 

[ericzhang]

This paper is proposed by engineer of Mediatek,
and i think it is a fully analog design.

 

[blowfish]

Hi,

Could i get the detailed explaination of that paper .
The tools used for entire vlsi design flow , from the begininig of simulation to final layout and GDS II format output .