Mar 31, 2004 #1 T talk2god Newbie level 2 Joined Mar 28, 2004 Messages 2 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 15 Hi, Can anyone help me out :?: I am designing a Digital-PLL with a center freq. of 2.048Mhz with 100 Hz spacing. I have a 66Mhz crystal and to achieve this step-size, the count value for the fractional-N counter is too high. How do i overcome this difficulty :roll:
Hi, Can anyone help me out :?: I am designing a Digital-PLL with a center freq. of 2.048Mhz with 100 Hz spacing. I have a 66Mhz crystal and to achieve this step-size, the count value for the fractional-N counter is too high. How do i overcome this difficulty :roll:
Jul 16, 2004 #2 H hanstarro Newbie level 5 Joined Sep 17, 2002 Messages 9 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 75 adpll main design difficulty I am about to implement an vhdl ADPLL in the next weeks. i found a good explanation about adplls at: http://www.aicdesign.org/2003%20PLL%20Slides/L050-ADPLLs-2UP(9_1_03).pdf example adpll code can be found at: **broken link removed** if you find out how good or bad the example implementation is let me know please. regards -hans
adpll main design difficulty I am about to implement an vhdl ADPLL in the next weeks. i found a good explanation about adplls at: http://www.aicdesign.org/2003%20PLL%20Slides/L050-ADPLLs-2UP(9_1_03).pdf example adpll code can be found at: **broken link removed** if you find out how good or bad the example implementation is let me know please. regards -hans
Jul 16, 2004 #3 S Serg_SV Member level 3 Joined Jun 30, 2004 Messages 66 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 429 adpll Zarling has very much devices for decide your problem.