Thanks,Zerro. And until now my design based on FPGA can track CW signal,but the frequency resolution in the PLL how to be improved,I wanna 1Hz in my design,but now it is only 1KHz. And I have tried to improve it without caring locked time,but it failed.Can you give me some advice?Hi Lin,
Costas loop is for carrier recovery in receiving supressed-carrier signals. For instance, for demodulating Double Side Band in analog communications, or BPSK in digital communications.
For track CW you can use a PLL.