Measurements are not made while DACs (U5 and U6) are operated. Is it still nessesary with filtering?simce said:2. Use of resitor and capacitor (RC filter) or LC filter on VDD of U5 and U6 to reduce digital noise from U5 and U6 injected into analog voltage during operation of DAC.
Yes the FPGA is configured via USB->JTAG inteface at each power-up.simce said:3. How FPGA is cofigured (only via USB/JTAG) or somehow else? Does it has internal configuration memory?
Yes, a short circuit should be mounted, if no microcontroller and LCD is connected to ITX5.simce said:Another question about PWS:
Power is drawn from USB, goes through TRACO DC/DC convertor and goes to 3.3VDGEN and to ITX5, but from where comes 3.3VDG? Does shorcut is supposed to be placed between 3.3VDGEN and 3.3VDG on ITX5?
Please read the previous posts in this topic.se06745 said:You divides the input signal 1/40. I think that it is a lot. ¿Can´t be 1/10, 1/50 1/100? And select one of them?? (Your first schematics was like these)
This was allready discussed, read previous messages.It's necesary to isolate all external lines (jtag, usb)??
You can power DSO from separate power supply and not from USB.This way you will avoid use od TRACO DC/DC convertor and optocuplers.It's a little expensive using DC/DC to islate USB power of Scope power??
This is more predictible solution and has less unexpected and unpredictable capacitances.(Your first schematics was like these)
I'm not sure what happens when digital informations are stored in DAC and output signal is stalled. If nothing is happening (if internal digital logic is driven by SCK) than this filtering is not necessary.Measurements are not made while DACs (U5 and U6) are operated. Is it still nessesary with filtering?
I've noticed that FPGA is configured via USB->JTAG, but what about stand alone version? It has to be configured by microcontroller or similar "device". I can not see any interface for this configuration or again JTAG via ITX5 will be used?Yes the FPGA is configured via USB->JTAG inteface at each power-up.
Yes the FPGA should be programmed via the microcontroller and an external flash/eeprom.simce said:I've noticed that FPGA is configured via USB->JTAG, but what about stand alone version? It has to be configured by microcontroller or similar "device". I can not see any interface for this configuration or again JTAG via ITX5 will be used?
Do you think about optocuplers used in USB isolation?I also have some other suggestions for changes to replace the opto-couplers with other less expensive, faster and cheaper devices which are based on another technology, but this will wait a little.
Yes, I think it would be a good idea to replace them with a NVE IsoLoop IL716 and an IL717 Digital Isolators.simce said:Do you think about optocuplers used in USB isolation?I also have some other suggestions for changes to replace the opto-couplers with other less expensive, faster and cheaper devices which are based on another technology, but this will wait a little.
The MAX4108/MAX4109/MAX4308/MAX4309 op amps combine ultra-high-speed performance with ultra-low-distortion operation. The MAX4108 is compensated for unity-gain stability; the MAX4109, MAX4308, and MAX4309 are compensated for minimum closed-loop gains (AVCL) of 2V/V, 5V/V, and 10V/V, respectively.
The MAX4108 delivers a 400MHz unity-gain bandwidth with a 1200V/µs slew rate. An ultra-low-distortion design provides an unprecedented spurious-free dynamic range of -93dBc (MAX4108) at 5MHz (VOUT = 2Vp-p, RL = 100), making these amplifiers ideal for high-performance RF signal processing.
These high-speed op amps feature a wide output voltage swing and a high-current output-drive capability of 90mA.
But the Input bias current is too high as monnoliv wrote in the last post.simce said:AD8057_8 input resistance of 10meg, 2pF, slew rate of 1000uV/s, gain flatness of 0,1dB till 28MHz. These are better characteristic than AD8065_6
Yes, you are right, i saw only input resistance of AD8057 that is 10meg and supposed that it is qute enough for this application, but...But the Input bias current is too high as monnoliv wrote in the last post.
It has to be a JFET or CMOS input opamp. Both JFET and CMOS types has very low input bias current.
I think that PWS has to be altered in order to use external power supply (from battery or mains adaptor). I think that on some laptop computers USB driver won't supply enough power when computer is supplied from its battery. Or power save modes has to be altered on computer. I had similar problem using external HDD through USB2.0. When computer is powered from mains power no problems are present, but when computer is battery powered usb driver does not activate hdd after enumeration.The DSO's +-3.3Vcc are just in between these ranges and TI doesn't make any JFET or CMOS opamps for +-3.3Vcc.
You should just consider that it's a bias current, like the bias current of a bipolar transistor. The impedance of 10Meg is a small signal impedance that occur when the input is biased correctly.This is very strange for me? How can OpAmp be with 10meg input resistance and bias current of 3uA? Vin=10e+6x3e-6=30V !!!
Maybe this 10meg's are calculated for common mode and not diferential (there are no informations in datasheet about this matter)?
simce said:I think that PWS has to be altered in order to use external power supply (from battery or mains adaptor). I think that on some laptop computers USB driver won't supply enough power when computer is supplied from its battery. Or power save modes has to be altered on computer. I had similar problem using external HDD through USB2.0. When computer is powered from mains power no problems are present, but when computer is battery powered usb driver does not activate hdd after enumeration.
Yes i know but sometimes USB driver can refuse high power requrements, more often if you have another device on USB port(mouse, keyboard or....).Normally USB is specified to deliver 500mA at a port
I'm focusing on input amplifier. If we use other power supply we can deliver +/-5V on opamps that have better characteristics.But I think we should wait to focus on thisuntil some of the other problems are solved.
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