digital logic necessary for the specification

[sun_ray]

Within 20 clock cycles maximum five times we can assert high an output named Activate. Again each time the Activated is asserted high, starting from that time instant maximum five times Activate can be asserted within 20 clock cycles of assertion of activate. Same will continue each time Active is asserted. Can anyone suggest a digital logic for this?

Regards

 

[barry]

Can you restate the question or maybe draw a timing diagram; it's not really clear what you are asking.