Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Redrawing so we can easily see the registers feeding each other without all the crossing wires.
Oh, look it's a register feeding a register and the output of the last register is feeding the input of the first register.
Looks like a divide by 2 (as long as there is a reset, which is not shown).
Now on to your question, with the tclock_skew of 1ns it won't work, once that skew gets added/subtracted you can no longer meet the setup or hold of one of the flops as the result of any calculation will end up 0 ns. (i.e. -1 ns of slack)
If you skew the clock in the other direction the problem just shifts to the other register.