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Digital logic design problem

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ykishore

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quest_flop.gif



Will this design work satisfactorily?
Assumptions: thold = tsetup = tclock_out = tclock_skew = 1ns.
After reset A = 0, B = 1
 

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Redrawing so we can easily see the registers feeding each other without all the crossing wires. :)
Capture.JPG

Oh, look it's a register feeding a register and the output of the last register is feeding the input of the first register.
Looks like a divide by 2 (as long as there is a reset, which is not shown).

Now on to your question, with the tclock_skew of 1ns it won't work, once that skew gets added/subtracted you can no longer meet the setup or hold of one of the flops as the result of any calculation will end up 0 ns. (i.e. -1 ns of slack)
Capture2.JPG
If you skew the clock in the other direction the problem just shifts to the other register.
 

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artmalik

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seems like an academic question?....don't think anyone will design this kind of circuit
 

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