Digital Filter Implementation Plz help.

[Mirzaaur]

hi all,
I need to implement FIR Filter for long tail of a pulse. I can do it with trational electronics filter but designing and implementing in verilog is a little confusing to see the starting point.

any good example or website which can guide me about design and implement process for FIR for FPGA.

thanks

 

[bangash]

use matlab 7 filter design tool. it also has option of generating verilog code. also code composer for xilinx ise

 

[salma ali bakr]

use matlab for the coefficients
then you can make a structural design for the filter which would have:
-delay unit (which would take the inputs from the ADC)
-ROM unit for the coefficients
-multiplier
-accumulator
-buffer
-FSM which would control the shift of the inputs and their multiplication with the coefficients and the buffer output and the accumulation control and the whole operation of the ADC in order to be always prompted when it finishes conversion