Digital Design Questions

[ustc23]

Suppose we have a pipeline which will process the data in 3 cycles. Sometimes the source may have no data to send out, and sometimes the sink may not be able to receive data. Define the interface signals first, and then design the internal control logic. We must keep the throughput 1 data/cycle, and if there are any possibilities the source shall always be able to send out its data.)


Pls reply to my question.

Thank you.

best regards,
Eric

 

[sree205]

Hi,
I'm not much of an expert in pipelining, but from what i can infer from the explanation of pipeling in computers, there is a compromise when designing a pipeline. That is the initial latency that has to be put up with when the first data passes through the pipeline.

Incase of sparse transfers, it maybe possible to provide a fastpath to the destination, but this will involve additional logic along with the pipeline and a constant polling of the data. I've not come across any designs which do this as well

To get a brief idea of pipelining, this link helps.

**broken link removed**

 

[yx.yang]

ok, you may need a buffer at the end of yur pipeline to balance the source/sink bandwidth. The depth of the buffer will depend on the source and sink's bankwidth characteristic.