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# Digital Chebyshev Filter Design help ->

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#### neuralc

##### Full Member level 4
Hello all,

I'm trying to design a lowpass Digital Chebyshev Filter IIR to get the average of sinesoidal wave with some cut's from a triac.

To do that I try to use Filte.r Solution.s but if I specify 10 sig bit (to use a 10 bit ADC of 16F870) I get saturation on the filter ...

Some one have tips to do that.

Thank's

NeuralC

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In your case I think there is problem with compiler. 10 sig digits from FS don't mean 10bit. 10bit it mean ~0.001 so only 3 or better 4 digits are enough. I think problem could be that compiller doesn't know what to do with so many digits, or maybe you should declare constants as float, or with conversion 10bit from A/D --> float (I think you use floats). I think before you start thinking about filter, check calculations (calculate what should be and then check simulated values).
On the other hand check FS response. I've simulated circuit in P*rotel and there were different responses than FS (about half of decade !!!). But there were no problem with digital filters

KamW

Hi neuralc

you can find a good background on the subject in the book of Oppenheim and Schafer 'Discrete-time signal processing'.

As I have not used Filte.r Solution.s, I cannot say nothing about it. I will give some general ideas on a method to avoid saturation.

Saturation problems appear depending on the arithmetic you are using. With floating point there should not be any problem, so I imagine you are using fixed point arithmetic (e.g. 16 bits) with 10-bit input data aligned towards less significant bits (this is important).

I imagine you are using a cascade of second order sections. You can calculate (or get by simulation) the maximum gain of the first section (at the peak of its frequency response), and with that, the maximum input amplitude allowable for don't saturate that section. If this input amplitude is lower than that you expect, you have to scale (attenuate) the input in orden to avoid saturation.
You have to proceed in the same way with the other sections of the filter. At each stage, attenuate the output of the previous one if needed. Don't attenuate too much, in order to preserve precision.
This method assures that you will not have saturation with any sinusoidal input. (There are other criteria and methods, but this one is ok).

I hope this help you. If you need more details, let me know.
Regards

Z

<font size=-1>[ This Message was edited by: zorro on 2002-01-31 17:00 ]</font>

ThX all,

KamW:
In FS when you go to discrete transfer function, and you select "unsign fix bin" the label sig digits are changed to sig bits, so I tink that I'm correct (10 sig bit's for a 10 bits ADC).
Other strange thing it's wherever you use Unsign Flt Bin or Unsign Fix Bin the code generated by FS use always floating point variables!

Zorro:
My knowledge about IIR are very poor; when you speak 'aligned towards less significant bits' what you means with that? (the 10 bits are aligned to left or to right within the 16 bit word?)

You know some app (not FS) where we can simulate the IIR filter and automatically get the C code for it's implementation?

ThX

NeuralC

Hi NeuralC,

Answering to your question, I intended to say that the 10 bits should be aligned at right (occupying the lower portion of a 16-bit word). The remaining 6 bits are the extension of the most significant (sign) bit of the 10-bit value. Because the first 2nd order section can have a gain greater than unity, if the input is strong you risk to get saturation at the output if the value is aligned at left (toward MSB).

Are you working with a C source code? If so, you can send it to me (with the desired characteristics of the filter) in order to take a look and help you...

Regards

Z

Hi NeuralC,

thinking again at your application, maybe there is something better and easier you can do if what you need is to measure the mean value of a periodic signal.

Sum the samples over an whole period (or an integer number of periods). It doesn't matter at which phase of the periodic signal you start. In this way, you will have an average of the signal over a cycle multiplied by the number of accumulated samples. If the sampling frequency is a multiple of the periodic signal, the measurement doesn't have ripple.

If you do that continiously at avery cycle (or N cycles), this is equivalent to use a FIR averager filter whose impulse response is a rectangular window followed by a decimator (downsampler). The transfer function has zeroes at the fundamental frequency and at all of its harmonics, so no ripple.

This method is easy and very fast, as all you need is to perform sums (no products). The only caution is that you have to use an accumulator long enough in orded to avoid saturation.
Regards

Z

Hi neuralc
You are right, there is possibility to truncate to number of bits, but I think it do not work. I check FS and found, that if I use signed or unsigned, there are always floats, and NEGATIVE numbers. It is very interesting property of FS isn't it maybe it is problem with c*r*a*c*k.
but return to your application. I always simulate filters parameters in VEE. So if you have problems PM FS file, I could check how it works.

Hi,

I have think in the solution of make a sum of all samples in a period and at the end make the division. The problem that I find its the fact that each sample can reach the value 3FF, so with a 16bit word i can sum a maximum of 64 samples (that’s are enough?). Each cycle have a period of 10 mS (100Hz), with a sampling frequency of 6400 Hz, no ripple? From cycle to cycle I have to sum previous value with actual and make division by tow?

My main problem it's the time that the 16bit division takes,(I'm using a 16f870 at 10 Mhz(400 ns)) ... do you know asm or C code to improve that?

Thanks for help,

NeuralC

Hi NeuralC,

the problem you mention (maximum number of samples in order to assure no saturation) is the subject I refered to when telling that you sould have the caution to use an accumulator long enough. If you are programming in C, use a variable of type long for the accumulator (be sure that your compiler uses 32-bits for long variables). If you use assembly language, use multiple-precision (24 or 32 bit) arithmetic.

Division is no problem if the divisor is a power of two: in this case the division is just an arithmetic shift (e.g. divide by 64 shifting 6 places at right). In order to preserve precision, you can perform rounding (rather than truncation) summing 1 (increment by unity) the accumulator before the last shift.

Even if the rectified waveform has 100 Hz frequency, it is preferable to sample a complete 50Hz period (or an integer number of them) because the two half-cycles don't have to be identical.

For example, if your sampling frequency is 6400 Hz, in one cycle of 50 Hz (20 ms) you have to sum 128 samples. After summation, the accumulator contains the average of the waveform multiplied by 128, and if you want this result in the same scale factor than the original signal you will shift it 7 places at right. But depending on what you are going to do with this result, maybe you need a different scale factor, so maybe you have to apply a different number of shifts.

You don't need to average a measurement with the previous one from cycle to cycle. You can do that, of course, and you will get a different filtering characteristic.

I hope this help. Stay connected.

Z

Hi NeuralC
With simple calculation in your clocks (6400Hz with 10MHz clock)it could be found, that there is time only for 2 multiple or one division per point in floating point maths. I think there is "filter" which could solve your problem. If you know frequency, shape and phase of signal you could use correlation techniques (so caled matched filtering) it need only one multipe and addition per point (with table). Or if you dont know phase, you should use complex calculations (you need twice calculations). It is very effective and fast method I've used. For more information check https://www.dspguide.com chapter7. (I've seen copy somewhere in FM1 )

Hi NeuralC
With simple calculation in your clocks (6400Hz with 10MHz clock)it could be found, that there is time only for 2 multiple or one division per point in floating point maths. I think there is

Hi all,

Zoro:

My idea of sum the average values from cycle to cycle it's because the system where the filter will be included it's to control the average of tyristor controlled wave. So if I sum the values I can see how the output it's changing and correct it to the desired value.

KamW :

Speaking again about FS, now we don't need the cr@ck for it, go to this post and get the licence:

but either with this the C code generate are always with float ....

ThX

NeuralC

Hi NeuralC,

On 2002-02-07 14:06, neuralc wrote:
.....
My idea of sum the average values from cycle to cycle it's because the system where the filter will be included it's to control the average of tyristor controlled wave. So if I sum the values I can see how the output it's changing and correct it to the desired value.
.....

It's ok. In this way you gan get a better measure of your variable (the average of the wave).
You can do an average of a number of the last cycles, or another method is to apply a digital filtering as this one:

Y = ((Y << N)-Y+X) >> N;
X = Y;

where X is the input (the value obtained by summing samples on the last cycle), Y is the output of this filter and N is a number of shifts that determines the time constant of the filter.

This is equivalent to perform a one-pole lowpass digital filtering with unitary gain, and time constant -1/ln(1-2^-N) times the sampling period of this filter (not the inverse of the sampling frequency of the signal i.e. 6400 Hz, but of the frequency at which this algorithm is performed, i.e. 50 Hz).

You should take into account the characteristic of this filter in your closed-loop response. You could use it for tuning the response and compensate for stability.

Regards

Z

<font size=-1>[ This Message was edited by: zorro on 2002-02-07 16:11 ]</font>

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