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digital asic design flow. flow is better? why?

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cosmosd

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digital asic design flow

hi we are desiging a small digital system that include a cpu ,and two IPs with AHB bus, i am a little confused about the design flow:some one said i should synthesis the whole design in the DC , and some one told me that i should partition my design in the SOC ENCOUNTER, and then desgin the blocks separately. so I want to ask which flow is better? why? Thanks.
 

ljxpjpjljx

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Re: digital asic design flow

first your IP should be verified in UVE ! Then do a top level synthesis and run fullchip simulation!
 

Syswip

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Hi cosmosd,

If your design is less then (... lets say) 200k gates and you don't have any black box in your design then use top down flow. It is really easy.


first your IP should be verified in UVE !

ljxpjpjljx could you please tell me what is it?

Thanks

Tiksan,
https://syswip.com/
 

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