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So formal verification can be accomplished by LEC tools. But some persons say formal verification is something different than LEC. That was even in contradiction to my earlier idea THAT "Logic Equivalence checking(LEC) is a Formal verifcation tool". I FIND U ALSO THINKS THE SAME.
Some people thinks formal verification is related to functional verification. I do not understand how this is true. Do u have any idea of this?
Do you think formal verification can mean something elec othe than equivalence checking of two circuits/systems.
Property checking is also a part of Formal Verification.
Your statement : Formal verification is related to Functional Veriifcation
This can be true, but will give you a scenario where the above statement can be true.
Lets take you have implemented an algorithm for certain functionality and you have completely verified the functionallity with gate level simulation and good coverage of tests are done this algorithm written in RTL. But there was a change in requirement w.r.t Area/Speed. Now you implemented different algorithm keeping in mind of the same functionality.
Instead of running your new algorithm through Simulation, you can simply perform LEC on these oldd agorithm and new algorith. This way you have done functional verification of your new algorithm.