Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

differential trace impedance calculation

Status
Not open for further replies.

Veronika

Member level 2
Member level 2
Joined
Mar 30, 2012
Messages
51
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Visit site
Activity points
1,651
Hello!

I am confused about the correct PCB stack-up for 100 Ohm differential trace impedance.
Can you describe me the basic rules for this and advise relevant links?

For example, I have differential stripline signals, which should be 100 Ohm impedance.
Dielectric thickness may vary, but at the moment I have 4mils.
Trace thickness is 0.6mils.

So I need to choose the correct trace width/spacing, am I right?
Previously I was used 5mils width and 6mils spacing differential traces.
But when I put all these values to some calculator it gives me only 72 Ohm of differential impedance.
What could be wrong and what should I change in my values in order to have about 100 Ohm impedance?
Should I trust to such kind of calculators?

Thank you in advance!

Veronika
 

How many layers is the board, and what is the allowable tolerance on the impedance figure as a percentage.
 

How many layers is the board, and what is the allowable tolerance on the impedance figure as a percentage.

The PCB will have 16 Layer in total.

About the tolerance I have read only this requirements:
"The data signal traces should be designed for controlled impedance. Single ended signals are 50 Ohm and LVDS signals are 100 Ohm differential."
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top