Differential signasl in DDR DRAM like clock

[sun_ray]

For a DDR SDRAM there will be two clocks according to specification named, ck_t and ck_c and they are called differential clock in the specification. How to take care of these two clocks in the design phase. Should we define two clocks named ck_t and ck_c or we should define only one clock named ck?

For a DDR SDRAM the specification defines the strobe signal also as differential signal named DQS_t and DQS_c. How to take care of this two strobe signals while designing? Should it be defined as one signal or two signal in the RTLs? Please advise.

 

[sharath666]

The PHY will take care of these signals. At the controller level, there is only one clock. Generate the write enable signals to the PHY correctly to ensure that DQS is generated correctly.