Differential Pair and ICMR

[CAMALEAO]

Hello guys,

I was reading the 2-stage opamp chapter in Sedra&Smith book when I came across with the ICMR concept. The input diff. pair is a PMOS.

They say in there

Consider the situation when the two input terminals are tied together and connected to a voltage Vicm. The lowest value of Vicm has to be sufficiently large to keep Q1 and Q2 in saturation. Thus, the lowest value of Vicm should not be lower than the voltage at the drain of Q1 (-VSS + VGS3 = -VSS + Vtn + VOV3) by more than Vtp , thus:

Vcim ≧ -Vss + Vtn + Vov3 - |Vtp|.

I can't understand what they mean should not be lower than the voltage at the drain of Q1 by more than Vtp. I know that the NMOS current mirror needs some voltage to be in saturation, say 150mV. I know that Vgs = Vov + Vth, say Vov = 50mV (for weak inversion) and Vth around 500mV. Why in the equation the |Vtp| is shown?

Regards.

 

[egni]

Hi,
lets answer your questions bottom up

Why in the equation the |Vtp| is shown?

well because:

the lowest value of Vicm should not be lower than the voltage at the drain of Q1 (-VSS + VGS3 = -VSS + Vtn + VOV3) by more than Vtp

Vcim ≧ -Vss + Vtn + Vov3 - |Vtp|.

I can't understand what they mean should not be lower than the voltage at the drain of Q1 by more than Vtp. I know that the NMOS current mirror needs some voltage to be in saturation, say 150mV. I know that Vgs = Vov + Vth, say Vov = 50mV (for weak inversion) and Vth around 500mV.

- - - Updated - - -

sorry, clicked the sent button accidently...

In a way you answered your question yourself but I will tried to find different words...
what they mean with should not be lower than the voltage at the drain of Q1 by more than Vtp? This is simply the condition for the PMOS to stay in saturation.
To be in saturation the channel needs to be pinched off on one side. The channel below the gate only exists if the voltage difference is bigger than Vth (considering the right polarity...). So to remain in saturation the voltage difference between gate and one side (which is then referred to as drain) is not allowed be bigger than Vth.

As you stated: to determine the absolut allowed minimum value for Vcim, you start at Vss. Considering the voltage needed for the current mirrow (also to be in saturation) you come up with a maximum value at the drain of your input/diffpair transistor. You substract Vtp which gives you the minimal allowed value of Vcim. If Vcim would further decrease both sides of the transistor would be "on" = " full conducting channel below the gate" so no pinch off on one side and hence no saturation.
I hope it becomes clearer now

P.S. What I am a little confused about is the first minus in your equation: Vcim ≧ -Vss + Vtn + Vov3 - |Vtp|.
Vcim ≧ Vss + (Vtn + Vov3) (=Vgs for the current mirrow) - |Vtp|

 

[CAMALEAO]

Hi egni and thanks for you reply.

Regarding your comment about the channel and the need of Vth, that's true and I know that but we learn that Vgs>Vth precisely for that.

Now, if you look to the traditional OPAMP with PMOS input pair transistor, and the CS on the second stage, if you start from the VSS (BTW the - behind VSS is because they are assuming you have connected a negative voltage source on the bottom) you will pass by the current mirror and then they climb the PMOS through the Drain. That's where the other Vth comes from. After doing some basic KVL to a PMOS transistor I concluded that the Vth that is shown on the expression is because the go from the PMOS drain to gate, being the voltage VDG = Vth. That's why.

Thanks for your effort on answering to my question.

Regards.