Differential Pair 2D Layout

[ytass]

Hi there,

This is my first time doing a differential pair layout, and I am hoping to gain some helpful pointers. My partially complete differential pair is shown in the attachment (screenshot). I am using Cadence Virtuoso.

My transistors are W/L = 56um/4um. I am using the 2D structure
dAsBdBsAd
dBsAdAsBd

where d = drain, s= source, and A and B are the inputs of the diff pair (NMOS).

My question is, is it ok to route the metal2 wires for the inputs like I have done? I am routing them over the top of other met1 contacts.

I am not sure how to route the drain connections. I would really appreciate some help here.
Please provide any other suggestions.

Do I need to add dummy transistors? If so, how do I connect the gates and the source connections of those transistors?

Thank you very much.

 

[road_0506]

...

 

[ytass]

Thanks for the reply, but with no explanation about the layout, it isn't too much help. The layout that yuo have provided is very complex and it is difficult to read all of the layers. Can you please provide more information, thank you.

 

[laglead]

why so complexed? Quad structure is ok.

 

[ytass]

What do you mean by quad structure?

 

[laglead]

It is AB
BA
simple is the best.

 

[ytass]

Thanks everyone for your replies.

So
AB
BA

would have matching performance as good as
ABBA
BAAB
?

Or is the reason that people use
AB
BA
because the routing is easier?

Are there any hard and fast rules for the routing of the drain and source connections for the
AB
BA
structure?

 

[ytass]

In my design I also require 2 x 2u/9u PMOS differential pair (CMFB circuit).
Please find attached my layout for a single 2u/9u pair.
I have arranged it as
AB
BA
with A = B = 1u/9u device.

Can someone please provide feedback on whether my layout is ok?
I have placed a substrate connection near the source connection, is this ok? Should I add more substrate connections, and if I do, where do I need to place them?

Can I route metal closer to the poly gates than i have?

Thank you.

 

[ersachinkalra]

Hi there,

I have somethings to say about this layout..

1) Poly M1 contacts are not enough. put as many contacts as you can put...

2) Same hold good for M1M2 contacts..put atleast two whereever possible.

3) You can have both the rows apart and make the input connections in between two rows of the transistors ....In this way you can save routing length.

4) Special care is needed for input signals and they should be matched as critically as the two transistors....matching the input signals mean having same route length for both the signal.

5) If you route the input signals in between you can have a cross coupled type of routings. one more thing to consider here if the frequency is higher or the criticality of the circuit is higher then you should cross both the signals using metal layer difference atleast of two...suppose you are routing one signal with M1 and to cross that signal put M3 or higher for the other signal.

6) Dont put substrate contact like this..the better way is to make a ring of substrate contacts surrounding the transistors and connecting the sources to those contacts with the metal layer.

7) Always prefer to use dummies on both sides.


I hope these things will help..do let me know if you need more information...

feel free to write me at sachinkalra1982@yahoo.co.in

Regards,

Sachin Kalra

 

[thetas49]

Hi, "matching" is eliminating the effects of processing gradients across the wafer, any feature at any coordinate from the centre point of your pair will only be matched if there is another feature exactly the same at the opposing cordinate,

centre point 0, 0
feature at +10x +4y will be matched if there is another the same at -10x -4y

therefore AB
BA is matched

ABBA ABBA
BAAB is NOT matched is has to be ABBA

You should always consider "interdigitation" when the devices are small, cross coupling small devices can add unnecessarily to the routing complexity, simple is DEFINATELY best.

 

[sudheerkm]

put dummies man it is a good practise