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Differential dynamic comparator - latch comparator problem

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salma shabayek

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latch comparator problem

i am trying to simulate a fully differential dynamic comparator in 0.13um process, vdd=1.2v,
when the threshold is zero i have only one error when the ramp is falling below the zero( threshold)
attached is my simulation ; the ramp is the positive input,the purple line is the clock and the blue line is the positive output
the clock switching the pmos transistors has a delay of 200ps from the external clocks of the system

i also want to know if i want to adjust a threshold , what to do ?
i know we add 2 transistors with vthreshold=(Wref/Win)*Vref but I've read thats a theoratical rule...does anyone know whats the practical??

 

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