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If you mean postlayout simulation, we simulate to double check STA results (ensuring there were no bad constraints) and also to check what STA does not cover (asynchronous paths). We can simulate at any corner STA is run, since we need SDF to be generated, but normally only a subset of corners is simulated due to runtime.
"Corner" in the context of circuit simulation means "models" corresponding to extreme process conditions. These models include device (Spice) models, which are called "fast" (low Vt, high Ion), "slow" (high Vt, low Ion), and their combinations corresponding to independent variations of PMOS and NMOS device (fast-fast, fast-slow, etc.). Also, these models include BEOL (back-end-of-line) models - i.e. multilayer metal/dielectric stack parameters (layer thicknesses, dielectric constants, resistivities, etc.) - in which case they are called by possible combination of words "capacitance/resistance" and "best/worst" ("best" meaning lowest value of parasitic R and C etc.).
"Corner" modeling is supposed to "guardband" the design against process variations that happen due to manufacturing effects (i.e. variations over wafer or over chip, as well as wafer-to-wafer and lot-to-lot variations) and due to microscopic physical effects (i.e. doping density variation in the channel of MOSFETs due to discretness of implants and due to polycrystalline gate structure, line-edge-roughness of poly-Si gates, and so on).
"Corner" modeling results in an over-guardbanding of chip design (i.e. sub-optimal performance).