semtechno
Newbie level 4
fifo synchronizer
Hello Everyone!!
I'm new to this forum and also a new entraint in the VLSI industry. I'm working with a design in which signals from different clock domains are interacting and I need to know the logic for designing different types of FIFO Synchronizers. Can anyone help me with a logic for FIFO Synchronizer for different clock domains like :
1> Plesiochronous clock domain.
2> Mesochronous clock domain.
3> Isochronous clock domain(where data stream has the timing information
embedded in it).
Hello Everyone!!
I'm new to this forum and also a new entraint in the VLSI industry. I'm working with a design in which signals from different clock domains are interacting and I need to know the logic for designing different types of FIFO Synchronizers. Can anyone help me with a logic for FIFO Synchronizer for different clock domains like :
1> Plesiochronous clock domain.
2> Mesochronous clock domain.
3> Isochronous clock domain(where data stream has the timing information
embedded in it).