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Different Clock Domain FIFO Synchronizers

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semtechno

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fifo synchronizer

Hello Everyone!!
I'm new to this forum and also a new entraint in the VLSI industry. I'm working with a design in which signals from different clock domains are interacting and I need to know the logic for designing different types of FIFO Synchronizers. Can anyone help me with a logic for FIFO Synchronizer for different clock domains like :
1> Plesiochronous clock domain.
2> Mesochronous clock domain.
3> Isochronous clock domain(where data stream has the timing information
embedded in it).
 

vlsi_whiz

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different clock doman

For synchronization you can use Asynchronous FIFOs which have two clocks - a read clock and a write clock. You have to be very careful in deciding the FIFO depth here as you need to prevent Buffer underruns and overflows. To synchronize other signals (signle-bit) you can probably use Dual Flip-flop synchronizers.
 

semtechno

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flop synchronizers

Thank you for ur reply....!
can u send me some docs or elaborate ur point in somewhat more details......or give me some reference website....if want to mail me some docs then u can contact me at: urtruth@gmail.com.
Once again thank you for ur reply...I'm eagrly awaiting ur reply.
 

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clock domain fifo

Hi all,
semtechno is that for Engineering end study project, master project, or simply a task in your work ?
 

semtechno

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plesiochronous clock domains

Hello master_picengineer!
Thank you for ur interest......this is for the work in which I'm working in the industry.....there I've to synchronize data transmission between two Meischronous clock domains......but before starting work on the actual problem I want to get myself acquainted with all types of situations & possible solutions.
 

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Hi again,
According to the research that I carried:
There are many solution but I didn't see any real implementation.
In fact I'm working on also and I am searching for the same information. I posted many times to get information about Mesochronous interconnect and I found only this IEEE papers.

Now, I'm looking for a very interresting book that study in depth these issues and solves problems of delays in interconnects and clock skew.

Try to find it
Skew-Tolerant Circuit Design
by David Harris

Please if you have it share it.

Keep in touch !

Don't forget to push the helped me button.
Thanks.
 

    semtechno

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semtechno

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Hello mater_picengineer!
Thank you for ur response.....the paper which u've mentioned is not available on the site as it is saying that it has been removed....so can u kindly mail it to me at my id; urtruth@gmail.com.....and the book which u've mentioned, do u've it or u r also searching it.

Thank you!
 

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The link is ok and paper are there. For the book I'm still waiting for someone to upload it.
 

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