differences of VHDL and Verilog HDL Netlist

[cheesent]

vhdl netlist diff example

Hello,

If I convert VHDL and Verilog HDL source codes to netlists, are there make any differences? like "VHDL netlist" and "Verilog Netlist"? Or we call them netlist only?

Chee Sent

 

[gliss]

There isn't much difference between VHDL and Verilog netlists.
There are also EDIF netlists.
And SPICE netlists for analog.

 

[rsrinivas]

Hi
there are differences.
Ur module names remain the same in the netlist and the instantiations in ur module are replaced by the technology available blocks outside ur module.
Hence a netlist is a technology dependent elobarated top level block.
so ur netlist would be much lengthy than ur verilog or vhdlcode.

cheers
srinivas

 

[cheesent]

Does that mean that netlist converted from verilog and VHDL are different even their functions are same?

For example, if I wrote CRC(cyclic redundancy check) in both verilog and VHDL. Then I convert both source codes to netlist. Are they make any differences?

 

[rsrinivas]

Hi
Yes ur verilog and vhdl netlists will be different.
verilog ex.
module add(a,b,c);
input a,b;
output c;
register c;
assign c<= a + b;
end

the netlist would be

module add(a,b,c);
input a,b;
output c;
register c;

//here goes ur instantiated adder from the library & how it does is technology
//and tool dependent like
add10_x u_add10_x(.a(in1), .b(in2), .c(out);
end

here will be ur description of the adder from the library.
say add10_x(in1,in2,out)
--
--
--
end add10_x

this adder will be in the library and it differs from design flow say FPGA and ASIC
the one what i told above is for ASIC design flow from synopsys Design Compiler.

Hope u have got the point.

cheers
srinivas

 

[cheesent]

Hello Srinivas,

Thank you very much.
I got what you meant.

Regards,
Chee Sent

 

[gliss]

What I mean is the VHDL and verilog netlist should be functionally the same, right?
You can convert from VHDL to Verilog netlists and vice versa and not loose functionality.