Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
A signal can describe registers or combinational "wires", a variable can do the same, depending on the VHDL code. They behave different in some situations and identical in others, depending on the context.
In other words, the question makes little sense without referring to specific VHJDL code.