It may be different width/length of transistor gates (different cell area, different cell delay, different power). It may be different transistor models - transistors with different voltage threshold. It may be different list of cells in libraries (more buffers, less types of flip-flops, special cells etc).
Interconnect characteristics usually the same - used the smallest width and spacing. The difference here is possible if different number of metal layers (1 or 2) used in the cell (cost is different cell area).
It may be radiation hardened library (special schematic and layout rules).