Difference between VHDL and Verilog

[ajeetsingh]

difference between vhdl and verilog

Hi all,
Please tell me difference between VHDL and VERILOG and using application area of both.
Thanks.

 

[sanjiv]

difference between verilog and vhdl

Difference between VHDL and Verilog please refer the attached file.

 

[matthew_wang]

differences between vhdl and verilog

Personal point:

VHDL is easy to behavioral modeling

Verilog is suitable for RTL coding

 

[Thomson]

difference between vhdl & verilog

Hi all,
Please tell me difference between VHDL and VERILOG and using application area of both.
Thanks.

you can search the paper written by Stephen Bailey-Technical Marketing Engineer

A very good introduction of VHDL/Verilog/SystemVerilog, especially their difference and pros and cons.

The title of this paper is "Comparison of VHDL, Verilog, and SystemVerilog"

Thomson

Good Luck

 

[salma ali bakr]

what is difference between vhdl and verilog

yeah, this paper is great....it always replaced the topics asking about these differences....

verilog is more close to transistor level modelling(low abstraction level)
while vhdl is more behavioural and abstract

Added after 5 minutes:

there is also...in the FPGA part of the forum
https://www.angelfire.com/in/rajesh52/verilogvhdl.html
chk that out....helpful also

 

[qin_hawk]

differences between verilog and vhdl

nice, thank you !!

 

[feroz]

difference betweenvhdl & verilog

thanksssssssssss

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[abhi_459]

1. Verilog is based on C, while VHDL is based on Pascal and Ada.

2. Unlike Verilog, VHDL is strongly typed.

3. Ulike VHDL, Verilog is case sensitive.

4. Verilog is easier to learn compared to VHDL.

5. Verilog has very simple data types, while VHDL allows users to create more complex data types.

6. Verilog lacks the library management, like that of VHDL.



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