Apr 26, 2006 #1 A ajeetsingh Newbie level 4 Joined Mar 16, 2006 Messages 7 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,328 difference between vhdl and verilog Hi all, Please tell me difference between VHDL and VERILOG and using application area of both. Thanks.
difference between vhdl and verilog Hi all, Please tell me difference between VHDL and VERILOG and using application area of both. Thanks.
Apr 26, 2006 #2 S sanjiv Member level 1 Joined Jan 4, 2006 Messages 40 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Activity points 1,614 difference between verilog and vhdl Difference between VHDL and Verilog please refer the attached file.
difference between verilog and vhdl Difference between VHDL and Verilog please refer the attached file.
Apr 28, 2006 #3 M matthew_wang Member level 3 Joined Oct 9, 2005 Messages 54 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,662 differences between vhdl and verilog Personal point: VHDL is easy to behavioral modeling Verilog is suitable for RTL coding
differences between vhdl and verilog Personal point: VHDL is easy to behavioral modeling Verilog is suitable for RTL coding
Apr 28, 2006 #4 T Thomson Full Member level 3 Joined Oct 15, 2004 Messages 181 Helped 4 Reputation 8 Reaction score 1 Trophy points 1,298 Activity points 2,400 difference between vhdl & verilog ajeetsingh said: Hi all, Please tell me difference between VHDL and VERILOG and using application area of both. Thanks. Click to expand... you can search the paper written by Stephen Bailey-Technical Marketing Engineer A very good introduction of VHDL/Verilog/SystemVerilog, especially their difference and pros and cons. The title of this paper is "Comparison of VHDL, Verilog, and SystemVerilog" Thomson Good Luck
difference between vhdl & verilog ajeetsingh said: Hi all, Please tell me difference between VHDL and VERILOG and using application area of both. Thanks. Click to expand... you can search the paper written by Stephen Bailey-Technical Marketing Engineer A very good introduction of VHDL/Verilog/SystemVerilog, especially their difference and pros and cons. The title of this paper is "Comparison of VHDL, Verilog, and SystemVerilog" Thomson Good Luck
Apr 28, 2006 #5 salma ali bakr Advanced Member level 3 Joined Jan 27, 2006 Messages 969 Helped 104 Reputation 206 Reaction score 21 Trophy points 1,298 Activity points 7,491 what is difference between vhdl and verilog yeah, this paper is great....it always replaced the topics asking about these differences.... verilog is more close to transistor level modelling(low abstraction level) while vhdl is more behavioural and abstract Added after 5 minutes: there is also...in the FPGA part of the forum https://www.angelfire.com/in/rajesh52/verilogvhdl.html chk that out....helpful also
what is difference between vhdl and verilog yeah, this paper is great....it always replaced the topics asking about these differences.... verilog is more close to transistor level modelling(low abstraction level) while vhdl is more behavioural and abstract Added after 5 minutes: there is also...in the FPGA part of the forum https://www.angelfire.com/in/rajesh52/verilogvhdl.html chk that out....helpful also
Apr 28, 2006 #6 Q qin_hawk Newbie level 3 Joined Mar 19, 2006 Messages 4 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 1,303 differences between verilog and vhdl nice, thank you !!
Apr 28, 2006 #7 F feroz Newbie level 5 Joined Jan 3, 2006 Messages 10 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,370 difference betweenvhdl & verilog thanksssssssssss Added after 22 seconds: thanksssssssssss Added after 13 seconds: thanksssssssssss
difference betweenvhdl & verilog thanksssssssssss Added after 22 seconds: thanksssssssssss Added after 13 seconds: thanksssssssssss
Dec 3, 2010 #8 A abhi_459 Member level 3 Joined Jan 22, 2006 Messages 57 Helped 3 Reputation 6 Reaction score 3 Trophy points 1,288 Location chd india Activity points 1,644 1. Verilog is based on C, while VHDL is based on Pascal and Ada. 2. Unlike Verilog, VHDL is strongly typed. 3. Ulike VHDL, Verilog is case sensitive. 4. Verilog is easier to learn compared to VHDL. 5. Verilog has very simple data types, while VHDL allows users to create more complex data types. 6. Verilog lacks the library management, like that of VHDL. Read more: Difference Between Verilog and VHDL | Difference Between | Verilog vs VHDL Difference Between Verilog and VHDL | Difference Between | Verilog vs VHDL
1. Verilog is based on C, while VHDL is based on Pascal and Ada. 2. Unlike Verilog, VHDL is strongly typed. 3. Ulike VHDL, Verilog is case sensitive. 4. Verilog is easier to learn compared to VHDL. 5. Verilog has very simple data types, while VHDL allows users to create more complex data types. 6. Verilog lacks the library management, like that of VHDL. Read more: Difference Between Verilog and VHDL | Difference Between | Verilog vs VHDL Difference Between Verilog and VHDL | Difference Between | Verilog vs VHDL