Difference between various terms used in system verilog

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telangamey_ei

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Hi,

I am new to System Verilog and just started reading it.

I am confused with the following terms:-

#1. Test, Generator, Agent & Driver this all looks same to me, what exactly is the difference in all of them.
#2. Similarly what is the difference in Score Board, Checker, Assertions & Monitor this all also looks same to me.

Can some one please explain this considering simple example of UART may be.

Please see that I already have gone through "testbench.in" website but it doesn't help me.

Thanks

 

The point of all these names is to encapsulate different components of a testbench in to separate components so that it becomes more re-usable and easier to maintain. The UVM introduces a standard way of separating these components so that it becomes easier to integrate components from different sources. Try the Verification Academy courses.
 
Thanks Dave for your reply.

I understand that each component is separated in S.V. to make it more re-usable.

But what every component should content & what it suppose to do? I am looking out for this explanation.

Could you please help to elaborate each component content & meaning?

Thanks
 

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