difference between using signals and variables in vhdl

[s3034585]

difference between signal and variable in vhdl

Hi
can any one tell me what is the difference between the hardware generated for a vhdl code which uses signals. If the same code is written using variables instead of signals.
Where can i get reading materails on this topic.
Thanks

 

[delay]

difference between signal and variable

Variables get updated right away whereas for signals to update certain other signals must be asserted or conditions need to be fulfilled before they can be updated usually at the end of a process in VHDL. When a signal is assigned a value, the assignment does not necessarily take effect because the value of a signal is determined by the processes (or other concurrent statements) that drive it. If several values are assigned to a given signal in one process, only the last assignment is effective. If several processes (or other concurrent statements) assign values to one signal, the drivers are wired together. The resulting circuit depends on the expressions and the target technology. It may be invalid, wired AND, wired OR, or a three-state bus. In many situations variables and signals can be used interchangeably if speed is not the issue. Signals usually are used for interconnection and busses (hardware), variables can be used for other operations such as counter increment. A variable would keep its value until a new value is assigned to it. Most HDL books and documents on HDL coding guidelines would discuss the respective uses of signals and variables at length. For synthesis, however, either must be used very carefully because the proper use can significantly affect the resulting hardware, its speed and performance.

delay (delayed by technology)

 

[kidman]

signal and variable in vhdl

During a delta cycle, any signals need to be value change will be put in a queue, one by one. In the update phase, all signals will be updated, and the simulation steps to next delta cycle.

If in current delta cycle, there is a variable need to be value change, it will be changed immediately, and all other signals, whose value change depends on the change of the variable will be put in the queue, waiting for update phase.

 

[xmizi]

signals and variables in vhdl

Is the variable and signal in VHDL comparable to wire and reg in Verilog?

 

[nand_gates]

vhdl variable vs signal

variable in VHDL can not be compare with reg and wire types in Verilog.

In verilog we can use reg type as variable along with blocking assignments.
here the reg declared variable will be global to module.(Unlike in VHDL
variables are local to process)

 

[masai_mara]

difference between variable and signal in vhdl

The use of variable or signal also impacts how your simulator handles the simulation. usually design with variables use less memory and also in modelsim the variable values cannot be traced like signals.

 

[wenty]

vhdl variable

variable update immediately, while signal update when achieve "wait" statement or at the end of process(if use sensitivities list), e.g. you can exchange two signals value like this:
x<=y;
y<=x;

 

[jetset]

vhdl variable signal

That's right, a signal changes it's value on every "cycle" of the process, but you can give several values to a variable inside a single process.

 

[negreponte]

signals and variables

the signal wait dt to update its value and then transmit its value.
For example if b<='0' and a<='1' the time t-dt and
b<=a; b will be equal to a after dt.
If we had variables the the value of b will be changed immediatelly.

 

[barkha]

variable signal vhdl

1.Signals are used to connect the design components and must carry the information between current statements of the design. On the other hand, variables are used within process to compute certain values.Variables must be declared inside a process
2. A variable changes instantaneously when the variable assignment is executed. On the other hand, a signal changes a delay after the assignment expression is evaluated. If no delay is specified, the signal will change after a delta delay. This has important consequences for the updated values of variables and signals.
-------------------------------------------------------------
below are the example in which a process is used to calculate the signal RESULT .

Example of a process using Variables

---

Code VHDL - [expand]
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architecture VAR of EXAMPLE is
signal TRIGGER, RESULT: integer := 0; 
begin
process
variable variable1: integer :=1;
variable variable2: integer :=2;
variable variable3: integer :=3;
begin
wait on TRIGGER;
variable1 := variable2;
variable2 := variable1 + variable3;
variable3 := variable2;
RESULT <= variable1 + variable2 + variable3;
end process;
end VAR

---

-------------------------------------------------------------
Example of a process using Signals

---

Code VHDL - [expand]
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architecture SIGN of EXAMPLE is
signal TRIGGER, RESULT: integer := 0; 
signal signal1: integer :=1;
signal signal2: integer :=2;
signal signal3: integer :=3;
begin
process 
begin
wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;
end SIGN;

---

-------------------------------------------------------------------
In the first case, the variables “variable1, variable2 and variable3” are computed sequentially and their values updated instantaneously after the TRIGGER signal arrives. Next, the RESULT is computed using the new values of the variables. This results in the following values (after a time TRIGGER): variable1 = 2, variable2 = 5 (=2+3), variable3= 5. Since RESULT is a signal it will be computed at the time TRIGGER and updated at the time TRIGGER + Delta. Its value will be RESULT=12.

On the other hand, in the second example, the signals will be computed at the time TRIGGER. All of these signals are computed at the same time, using the old values of signal1, 2 and 3. All the signals will be updated at Delta time after the TRIGGER has arrived. Thus the signals will have these values: signal1= 2, signal2= 4 (=1+3), signal3=2 and RESULT=7.

 

[SkyHigh]

variable vs signal vhdl

As someone before me has already explained, Variable and Signal are used differently (in fact specifically) depending very much on:
1. Are you doing it for simulation for you to validate the functionality?
2. Are you doing it for synthesis and optimise your design to meet timing?

These questions determine which to use.

Here are some rules of thumb for those who are unsure of HDLs (VHDL & Verilog) and Synopsis:

1. Variable and Signal are synthesizable hardware.

2. Variable is used within a sequential component i.e. a memory device such as a latch, thus variable updates its assigned value instantly. Variable is most commonly used as a counter for decrementing or incrementing value in a FSM. A synthesised Variable is nothing more than a latch found in register because every component named by a Process is a sequential element. For more information, please read the popular textbook written by Randy H. Katz.

3. Signal is used globally within an architecture and it must only be declared in the architecture right in the beginning. Thus Signal is in fact a wire after synthesis with no memory element at all. Since Process performs sequential operation based on delta delay (unit delay), Signal only gets updated after a process. This is logically and physically correct because a wire connected to the output of the sequential component (a Process) can only be updated after this component has completed all its computational tasks.


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