difference between test bench code and original hdl code

[rashmi.imhsar]

Can someone tell me what a test bench actually is ? like I know that there is something called test bench code that is written to check the logic and flow of the code by verifying the output .

But modelsim does the same right? I dont understand the difference between test bench code and the original vhdl code. Can someone elucidate on this ?

Also steps to create a test bench code for my hdl code.

 

[TrickyDicky]

a testbench is HDL code - but it designed specifically for testing another piece of HDL code.
So you designed a memory block. How do you know it works? you write a testbench that produces a load of inputs and captures the output (and probably checks to make sure the output is what you expected).

Modelsim is just a simulator. It does nothing on it's own. It just provides an environment to run HDL code.

 

[rashmi.imhsar]

okay but why do we need to simulate the test bench code ? y not just simulate the original code in modelsim ? the original full code also gives the output value and wave forms when simulated right?

and the test bench code is simulated just like how a normal hdl code is simulated right? or should I change any settings in modelsim before running the test bench code?

 

[shahulakthar]

okay but why do we need to simulate the test bench code ? y not just simulate the original code in modelsim ? the original full code also gives the output value and wave forms when simulated right?

and the test bench code is simulated just like how a normal hdl code is simulated right? or should I change any settings in modelsim before running the test bench code?

Original code don't have any specific timing info on input signal High/ Low.

For example:
if you have reset signal you must specify in you testbench like

Reset <= '1';

wait for 10 ns;

Reset <= '0';

wait for 10 ns;


original code only say

reset <= '1'
do this
else
do that

 

[rashmi.imhsar]

ohh ok ok ... it basically takes care of the timing constraints that the hardware faces.

OK. so making a few modifications to the original hdl code gives the test bench code which should be simulated like how we usually simulate a normal code in modelsim right?

I read somewhere that I have to go to Design » Create VHDL Testbench . Where can I find this?

 

[TrickyDicky]

The testbench has nothing to do with the timing (unless its a timing testbench).

The module will have a set of inputs. If you dont provide data to those inputs, the design will probably provide no meaningful output.

So, going back to my ROM analogy from before - it will have a clock input and address input. If those are left unconnected (ie, you just load the memory module in modelsim) it will not provide a data output. You need a testbench to provide a clock and address to the memory, then you check the output.

The testbench is just more HDL code you write for yourself.

 

[rashmi.imhsar]

That was informative !

But, I just simulated the original code and got the output waveform as expected. So I do not need to use the test bench right?

 

[TrickyDicky]

If you got the results, then you must have created a testbench of some form, even if you drew the waveform yourself. Unless you have a magic design that has no inputs.

 

[ads-ee]

Or perhaps the OP used Modelsim force commands to stimulate their UUT?

Of course for a very simple designs like a counter this would be a viable solution as you only have to use two force commands to exercise the clock and reset inputs.