Difference between task and module in VerilogHDL

[ygdizzy]

I am master student of chip engineering.
i have question about verilog rules.

i studied a guide to Verilog, but i don't know what the difference between task and module is.
Both of them do something in tool.
If task is just subprogram like function in C language, task could be replaced with module.

plz answer my question. i need high-class engineer's advice.

 

[ahmad1954]

with task you can increase readability of your programs. also you can write a task and use it in different designs.

 

[dave_59]

They are two different concepts. If you are familiar with object oriented programing, a module is like an object; it is a container for signals and the behaviors associated with those signals. A task/function is just one of the many ways of modeling the behaviors of that object, a procedural method. Other ways of representing the behavior of a module is through continuous assignments or instantiating other modules.

 

[ygdizzy]

Thank you for your answer.
I received answer from my senior engineer.
He said "Task/Function will not be synthesized. Task/Function's purpose is not implementing hardware's function. As you see, task or function word can be seen only test bench code. Only module is synthesized in order to do hardware function."
Is it correct?

 

[dave_59]

Thank you for your answer.
I received answer from my senior engineer.
He said "Task/Function will not be synthesized. Task/Function's purpose is not implementing hardware's function. As you see, task or function word can be seen only test bench code. Only module is synthesized in order to do hardware function."
Is it correct?

Not correct. Most synthesis tools can synthesize functions and tasks. They are in-lined i.e. the code in inside them are expanded as if they were cut and pasted into place.