difference between synthesis with ISE and SynplifyPremier

[thkhine]

Hi,

I am trying the following two ways to generate the bit file for FPGA implementation.
(1) Synthesis with Synplify Premier
Implement Design and Generate Programming File with ISE

(2) Synthesis with ISE
Implement Design and Generate Programming File with ISE

When I implement as (1), there is no error with my verification.
When I use (2), FPGA implementation itself is ok. However, I couldn't do correct evaluation.
I don't know how to find the error.

Could anyone tell me the synthesizing performance difference between Synplify Premier and ISE.
What kind of synthesis set up should I care?

I appreciate for any help.
Thank you.

 

[dcreddy1980]

To check if there are any wrong optimizations in synthesis tool, do Formal verificationi.e. any Equivalence check tool (Example : onespin) on RTL vs Netlist(ISE).

The above step atleast confirms whether ISE is doing correct synthesis or not.

 

[thkhine]

To. dcreddy1980

Thank you for the advice.
However, could you tell me in detail about formal verification.
I am not familiar with that kind of verification.

 

[shanmugaveld]

You can verify the warning,note given by the ISE tool in the transcript, through that you may able to figure out the issue