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difference between stray, parasitic and coupling capacitance

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Junior Member level 3
Mar 23, 2002
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hi all,

as the name of the topic indicates, i want to know the difference between the stray capacitance, parasitic capacitance and coupling capacitance with ASIC as the referance. can any knowledgable person explain them to me?

thanks for listening to me.

Imagine that there are two wire wires in the same metal level on chip running in parallel. Than these two wires have a mutual capacitance and a capacitance to substrate. The first one is called coupling and the second one area. If you take into account only one wire its parasitic cap is made of a parallel plate component and a edge component. Therefore these caps are specified as fF/um^2 and fF/um. If a single minimum dimension wire has a total capacitance made of edge and area you can estimate the load of a buffer by calculating wire total wire lenght. If a second wire runs in parallel some of the cap is now redistributed to him. At 1 micron that made about 20%. At 0.1 micron this made about 80%. That is because the aspect ratios of the wires reverse. But now you can not rely on calculating your timing impact in your ASIC by measuring the wire lenght. In addition to that you have to verify that the buffer is strenght enough to reduce the noise introduced by coupling. That boost you up in a new dimension of verification problems. The cause is well known but the tools are far behind for million gate designs.

So, no question for coupling cap.

Parasitic cap means the cap to GND/substrate while the rest (Cgd, Cgs, etc.) called stray cap. Am I right?

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