DTA: a series of simulation vectors over time are applied during a Chip simulation. Chip simulation calculates the logic values, delay, timing even over time. The simulation will detech the timing falling path by using slack. for late-mode, slack is define as a substraction of required-time to arrive-time. It take a long to run and is very difficult to find out the true cause of failure even (mixed functional and timing problem). It is used for asynchronous logic.
STA: An analysis which work only a timing window. Because, data can't change its values within these windows. It is very complex to learn, but easy to debug and takes less time than to run. STA work best with synchronous logic. Nowaday, all EDA tools use the STA engines for timing viewers.
I will post some useful information later, coming soon!