Difference between signal and variable

[Binome]

Hi,
I've used signals (defined in the beginning of architectures) and variables (defined in the beginning of a process) to have local variables in process.
I'd like to understand the difference.
Thank you.

 

[Miralipoor]

Hi,
Beside argument about differences that you can get them with simple search, i add this statement
Almost signals converted to physical wire but almost variables are virtual facilities to manage those wires.
Regards.

 

[TrickyDicky]

Hi,
Beside argument about differences that you can get them with simple search, i add this statement
Almost signals converted to physical wire but almost variables are virtual facilities to manage those wires.
Regards.

This doesnt really make much sense. Both signals and variables can be infer wires, logic or registers, it depends how you use them.

The difference is that signals are scheduled to be assigned at some point in the future, variables are assigned immediatly.
for a signal assignment like this:

a <= b;

a will be assigned the value of b on the next delta cycle, as no "after n ns" was set. Also, within a single delta cycle, if multiple assignemnts are made, the last one will override all of the others:

process(clk)
begin
   if rising_edge(clk) then
    a <= a+ 2;
    a <= a + 3;
    a <= a + 20;
    a <= a + 1;
  end if;
end process;

so with the above code, a ends up as + 1 on every clock cycle, as all of the other assignements are overriden

for the variable assignment:

a := b;

a is assigned the value of b immediatly, within the current delta cycle. so with similar code to the above:

process(clk)
begin
   if rising_edge(clk) then
    a := a+ 2;
    a := a + 3;
    a := a + 20;
    a := a + 1;
  end if;
end process;

a ends up being +26 on each clock cycle, as all of the assignments occur immediatly.

 

[Miralipoor]

Your first part of code is not synthesizable so it is wrong in real work but it's syntax is still correct. Your second code is not describing hardware until you assign that variable to a signal.
Regards

 

[TrickyDicky]

Your first part of code is not synthesizable so it is wrong in real work but it's syntax is still correct. Your second code is not describing hardware until you assign that variable to a signal.
Regards

I dont know what code you are referring too. Both bits of code are synthesisable. the first one will create an adder that adds + 1 on each clock cycle.

Yes, the second needs a signal assignment, but the placement of that signal assignment will affect whether a is registered or not.

 

[p11]

can we treat both signals and variables as connecting wires between different functions? i mean then specifically when to use signal and when variable ? if i write a program in vhdl for programming xilinx fpga , then can we send a variable as an output to the fpga or we need to always use signals as output to fpga ?

 

[sharath666]

Variables are local to the process block where they are defined. Signals are valid throughout the entity they are defined.Examples of the former are loop variables (i,j...) while examples of the latter are registers.

 

[TrickyDicky]

You cannot connect anything between functions - function inputs are always constant.
But given your post, I think you were referring to processes? Variables must remain local to a process/function/procedure. You need to use signals to communicate between processes/entities

But it sounds like you're approaching it as if VHDL was software. VHDL is a HARDWARE description language. You need to know the hardware you are trying to create before you write the code. Have you drawn a circuit diagram of the circuit you're trying to produce? I highly recommend you draw the circuit before you write any code..

 

[p11]

ok , can we transfer the value of a variable to a signal?

 

[TrickyDicky]

Yes, but it has to be done inside a process. And remember, a signal can only be assigned inside a single process (but read in unlimited processes)

my_signal <= my_variable.

I have to ask - if you're a beginner, why are you considering variables at all? there is nothing you can do with variables you cannot do solely with signals. And I would highly recommend you do this, as you'reless likely to fall into the traps you can get with variables

 

[p11]

yes i am a beginner .U want me to use signals only , yeah thats a good idea..