[SOLVED] Difference between <= Relational operator and <= Non blocking assignment

[debasish_deka]

Hi All,
I am very new to verilog and got confused between the Relational operator <= (which is less than equal to) and the Non-blocking assignment operator <=.:bang:
I want to know how does the verilog compiler know that the variables on the either side of this operator means assignment operation not comparison or the vice versa.

 

[TrickyDicky]

It will depend on context. A simple

A <=b;

Is an assignment. But

If a <= b

Will be less than or equall

 

[debasish_deka]

Thanks Tricky Dicky,
Then how'll this code behave

if(a<=b)
    d<=a;

Actually I am from microcontroller programming background. To me it seems like (a<=b) evaluates to TRUE always and finally the value of b goes to d.
Am I right?

 

[rberek]

No, you are not correct.

All that bit of code says is that "if a is greater than or equal to b, assign a to d." The value of b is not changed by the comparison, and nor would it be in the microcontroller world. There is also nothing in that code to indicate that a<=b would always evaluate to TRUE. You have given no values for any of a, b or d so no assumption can be made as to the result of that comparison.


r.b.

 

[ads-ee]

All that bit of code says is that "if a is greater than or equal to b, assign a to d." The value of b is not changed by the comparison, and nor would it be in the microcontroller world. There is also nothing in that code to indicate that a<=b would always evaluate to TRUE. You have given no values for any of a, b or d so no assumption can be made as to the result of that comparison.

rberek, you've missed the point the OP was making, the OP thinks the if (a<=b) is an assignment a gets assigned b and the if is checking the assignment operation which is always true as b did get assigned to a.

if(a<=b)
    d<=a;

To me it seems like (a<=b) evaluates to TRUE always and finally the value of b goes to d.
Am I right?

Don't know how you would think this would be true for C, C++, Verilog, etc, Perl perhaps but certainly not Verilog or C.

To reiterate what Tricky posted:
It depends on the context.

a <= b; // assignment (notice it's on a line by itself with no "if" in front of it and it ends with a ";"), stick the value of b into a.

If (a <= b) // comparison of a less than or equal to b when true execute the next statement

assign c = (a <= b) ? d : e; // comparison of a less than or equal to b being true assigns c with d

Actually I am from microcontroller programming background.

Then don't use for loops, while loops, tasks, and functions until you understand how to write simple Verilog RTL that describes hardware using standard coding templates. This will save you a lot of grief and hopefully keep you from making the same mistakes so many others with a software background make when they try to learn what they think is the Verilog "software" language.

Regards

 

[rberek]

To be honest I wasn't sure how/why the OP made those conclusions but I felt it made the best use of my time explaining the correct interpretation rather than fall down a rathole trying to figure out the incorrect one.

Also I misinterpreted the following sentence:

and finally the value of b goes to d

I now see they meant to say that d gets the value of b rather than the reverse.

r.b.

 

[ads-ee]

To be honest I wasn't sure how/why the OP made those conclusions

You haven't used Perl much ;-)

 

[rberek]

I've used it a fair bit, I must just never have been confused by that. I have, however, been confused in lots of other ways!

r.b.

 

[dave_59]

It's very simple: the compiler uses the BNF to parse text token by token and recognizes what are called productions . A good example of this is the text

A <= B <= C

If you were to send just this text through a Verilog compiler, you would get the following error:
** Error: abc.v(1): near "A": syntax error, unexpected IDENTIFIER
That's because at the top level of a Verilog source file, there are only three productions available

source_text ::= { description }
description ::=
  module_declaration
| udp_declaration
| config_declaration

which basically means the first word in a Verilog source descriptions can only be one of module, primitive, or config. The compiler could not match any of the productions with the token "A", so it throws a syntax error.
Now lets send the following code to the compiler:

module test;
A <= B <= C

you would get the following error
** Error: abc.v(4): near "<=": syntax error, unexpected <=, expecting IDENTIFIER
Note the error is now on the "<=" token and not the "A". That's because inside a module_declaration, you are allowed any number of module_item productions, one of which could have been a module_instantiation like

A inst_name();

But there no module_item production that matches an identifier followed by '<='. So you get an error.

This process of parsing all your source text in productions keeps going until there is is no ambiguity left in what a token represents. Skipping ahead to a block of code that looks like

begin
  A <= B <= C;
end

The compiler is parsing a set of procedural statements, or statement_item productions. One of the production choices is

nonblocking_assignment ::=
  variable_lvalue <= [ delay_or_event_control ] expression

There is no expression production in a statement_itemso the first '<=' can only be matched as a nonblocking assignment construct. When the compiler parses the B <= C part of the statement, the only thing <= could match in an expression would be a less-than-or-equal operator.

Hope this helps.

 

[mrflibble]

Re: Difference between &lt;= Relational operator and &lt;= Non blocking assignment

Bonus points for having the patience to type what I thought. After 1 paragraph of typing I went "ah screw it, people just have to read the fine LRM" and pressed delete.

- - - Updated - - -

And speaking of reading the fine LRM ... just google "verilog 2001 lrm" to find the standard for verilog 2001. And you'll run into the SystemVerilog documentation as well that way. Or grab it here: