Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Difference between FPGA and ASIC

Status
Not open for further replies.

Elnegm

Member level 1
Joined
Jun 28, 2005
Messages
33
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,524
difference between fpga and asic

What is the main differences between FPGA and ASIC?
if anyone has an articles to explain that please upload it
THX
 

difference between asic and fpga

See this you will have all answers




eda_ak
... still learning
 

differece between fpga and asic design

FPGA - Field Programmable Gate array
1. FPGA are powerful and can be reprogrammed many times.
2. cheaper, therefore used for testing, but are slower, and cannot hold large designs...
3. FPGA's are used for developing design prototypes because they are reprogrammable hence saves time.It consumes more power,slower than ASIC as it used active elements as switches.Cost per chips is more.They consume more physical area.

ASIC - Application Specific Integrated Circuit
1. ASIC once programmed it is fixed.
2. much more expensive, it is not a very common practice to nessecarily prototype a design
on an FPGA
3. ASIC no active elements as swithces, hence less power used ,hence faster too.Designs proven on FPGA can be migrated to ASIC but cost more.This is done if chips are to be mass produced.
 

asic fpga difference

I guess many people are misunderstood, not just you. There was a period of time, when I was student, my lecturer told me that he got confused too because during the 60s to 90s, too many jargons in digital ICs emerged during the ASIC boom.

My knowledge is based on what I know and what I read, especially from some popular textbooks written by (1) Michael Sebestian Smith, (2) Weste & Eshraghian, and (3) Jan Rabaey.


ASIC is a general terminology to classify ICs built for application-specific, for a chip that only performs Turbo-Coding, Radix-4 FFT or etc.

FPGA is a type of ASIC but more oftenly called programmable ASIC that also grouped PLDs such as SPLDs and CPLDs.

ASIC, to be strictly called, is actually classified into several domains.
1. Full Custom ASIC such as Analog ICs, for example ADCs, Mixer, Amplifier.
2. Semi-Custom ASIC such as Cell-based, Standard Cells, Channel/Channel-Less SOGs or MPGAs.
3. Programmable ASICs such as FPGAs, CPLDs, SPLDs etc.
4. Standard ICs such as NAND, NOR, NOT gates etc found in 74-series.

PhD MSc DIC BEng (Hon)
Analog Devices Inc (Ireland)
 
  • Like
Reactions: arpkum

    arpkum

    Points: 2
    Helpful Answer Positive Rating
fpga asic design synthesis difference

You see different numbers to move from FPGA gates to ASIC gates.
It basically depends on the FPGA you use. The official number from
Xilinx is 6FPGA gates to 1 ASIC gate. It also depends on whether you
calculate the flipflops and LUTS together, or separate. I tend to count
flipflops and LUTS separate; using 8gates for the flipflops and a
variable number (depending on the FPGA) for the LUTS. Most modern FPGAs
–think Virtex and descendants, or Flex/Apex style FPGAs- scale to about
2-3 gates per LUT.
And then there’s the memory of course.

You should also read Bill’s text carefully. He states that the same
logic occupies approx. 40-100x the area in an FPGA compared to an ASIC.
Area being actual silicon, not gates

Added after 3 minutes:

hi forget to give u a link

see this link,this will help u

**broken link removed**
 

diffrence between asic and fpga

hi folks

the main difference from the aplication point of view is reusability. The FPGA can be reconfigured and can be put to use for another design thus making it versatile which is not the case with ASICs.

Ashish
 

big differences between asic and fpga

It's part of my thesis: descript ASIC to FPGA code comvert items. Hope to help U


Chip-level partition
In order to keep similar with ASIC structure, FPGA should take the same partition strategy as ASIC. In XXX project there take 3 sub-system partitions, so does FPGA.
 Gating clock
Because clock single in FPGA is too sensitive to be affected production some signal jitter, skew, glitch and noise, it should be avoided to use gated control clock. It can be used the gating signal as enable signal (CE) of flip-flop by two input MUX, one is Q feedback, the other is data signal.
 Internal latch
Unlike ASIC, internal latch of FPGA will cause some confusion. At low switching speed, there will import a new clock in one clock domain. Another disadvantage, while in high switch speed, the latch became pure combination logic, causing timing confusion. Adding pipeline registers if timing is hard to meet.
 Big Fan-out buffer
Pre-define internal logic cell have limited fan-out capability of FPGA associated with FPGA vendor’s process. For globe driver signal, clock, reset, big fan-out nets should assign to use internal big fan-out buffer. Sometimes it should be replicated same net in design for big driver capability.
GSR(Global Set/Reset) feature and GTS(Global Three-State) control are dedicated net to Xilinx FPGA series. When adapting a design to a Xilinx FPGA series, be sure to remove any ASIC-specific code associated with global reset, set and three-state operation. Replace them with Xilinx instantiated HDL components.

 Memory replaces
In FPGA implement, memory should be replaced by pre-define internal memory. Block-memory on chip should be instantiated as FSM, FIFO, LUT etc. While in ASIC implement, on chip memory is based on fabrication vendor’s standard memory cell, standard library, which is more flexible.
VirtexII FPGA can provided Block RAM, it also supports distributed RAM, which means the four-input LUTs can be used to implement a variety of memory type, including synchronous RAM, ROM, Dual ports, and FIFOs. This is quit different with ASIC for which RAM is synthesized from generic NAND. When adapting ASIC code for FPGA, it important to replace all gate-level memory functions with Core Generated ones, in this way, an efficient implementation of memory in FPGA is assured.
Another important issue when adapting ASIC for FPGA, the asynchronous memory can’t be implemented in FPGA when Core Generator involved. So the HDL architecture substitution is necessary.
 Arithmetic block
There should take balance strategy in speed and area. Specialization arithmetic IP in ASIC design has advanced structure used gate-level or transits-level model optimized. In FPGA design, vendor support some pre-define special arithmetic block, but it is limited. Also it could be implemented by FPGA structure, which cost more area. There is some arithmetic IP of design ware from synopsys, which can’t be implemented in FPGA directly with no performance reduced. In order to get high design performance, it is essential to optimize the code being suit to FPGA structure.
 PLL slice
Analog input PLL/slice could not be implemented in FPGA. There has digital PLL (name DLL) inside FPGA. In Xinlix device it is DCM module, which is implemented use self-increase address ROM.
 Vendor library replace
FPGA is based on LUT/LAM pre-define structure device. Different vendor supple different devices with different structure, FPGA synthesis is mapping design to special vendor’s device library. For more stable function design should replace vendor library. ASIC contains a sea of relatively undifferentiated NAND gates, whereas the VirtexII FPGA employs more highly-structured CLBs (Configurable Logic Blocks) and IOBs (Input/Output Blocks). Nevertheless, how effectively CLBs and IOBs can be utilized may depend on how the design is coded in HDL

Added after 9 minutes:

Ahead of last part:


There are key differences between the two types of silicon platforms in ASIC and FPGA that mandate specific features in the EDA tools we need to develop and implement the latest generation of FPGA. ASIC are conceived from scratch, while FPGA have a predefined architecture for a given family of devices. In ASIC point of views, the whole chip is all customers manage. All the sub-module, block, cell, gate are based on the process of back-end silicon implement. The coding style is free in ASIC domain. There are some different design rules between ASIC and FPGA coding style. This means designers must follow different HDL coding guidelines for each type of platform.
Complex FPGA design shares some commonality with ASIC design, in the sense that both sets of designers must account for timing, power, and other performance specifications. Designers of both platforms perform synthesis, RTL simulation and generate test benches. But, many steps are fundamentally different. The predetermined nature of FPGA drives a “use or lose” approach to features/capabilities. FPGA design, more often than ASIC design, must match functional requirements with the device architecture.
ASIC design consists of many disparate design tasks that are not part of an FPGA design flow. For example, the FPGA vendor has already taken care of clock-tree synthesis and boundary scan. FPGA designers also need not perform silicon verification or scan-chain insertion for test. Since most FPGA power up in a known state, FPGA designers do not have to initialize memory bits, latches or flip-flops. To their advantage, FPGA can also have embedded logic analysis capability for debugging a design.
As high-end FPGA encroach on ASIC performance, many advanced ASIC techniques are being adapted for FPGA design. The introduction of high-performance, multimillion-gate FPGA has forced designers to turn to physical synthesis and hierarchical floorplanning (commonly used methods within the ASIC design flow) to achieve design goals and to support incremental design changes without long place-and-route (P&R) run times. Coarse floorplanning alone will no longer suffice—both ASIC and high-performance FPGA need placement-based models to achieve timing closure.
Significant differences between the Xilinx FPGA Series and ASIC give rise to the differences in the way features are implemented. When adapting the ASIC design to suit FPGA, it is necessary to remove any references to ASIC-specific features and replace them with FPGA equivalents. In some cases, this will mean substituting code in HDL file; in other case, it will be a matter of selecting the appropriate switch in the Xilinx development software.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top