Re: Difference between Divide by n counter and clock divider
shwetha100: what you're describing is called a "shift register" not a counter. you can also divide the clock with the circuit you described, but it will by a %50 div by 6 clock.
the best way to figure out how it works is to to draw the circuit. label all the nodes (d1,q1,d2,q2 keeping in mind that q1 = d2 and so on) if you have n registers then qn will be your output, and draw all the waveforms including the clock. you must pick a beginning state for all of your registers (this will also determine the functionality) say setting them all to zero. so all the q outputs will be zero, and all the d inputs will be zero with the exception of d1, which is 1 because of the feedback inverter. the number of register stages is the number of clock cycles that it takes for that 1 to propagate through the shift register, and similarly, the number of cycles for the 0 to propagate. so in the end this gives you a 1/(2*n) divider not a 1/(2^n) divider.
let me know if that made sense!
Added after 1 minutes:
shwetha100: that's wrong, there's nothing asynchronous in this circuit. everything is happening in sync with the clock.