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difference between design compiler and prime time

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kinysh

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Hi:

except using different script.
I know one major difference between them is :
dc only use worst case timing
pt can analyze both best case & worst case.

any other difference ?

bests
 

lipton

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Primetime is more accurate and faster.
 

robin_su

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pt has case analyze but dc do not
 

dumeHCM

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Design compiler is a synthesis tool
Prime time is a verification tool (timing requirement)
 

tutx

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dumeHCM said:
Design compiler is a synthesis tool
Prime time is a verification tool (timing requirement)
Synthesis and Verification, what is the main differences between them? Sometime, I make two in one. It's really true or not ? I seem that synthesis became one part of verification (!).
 

gaonkc

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primetime is static time analysis(faster)

dc is dynamic time analysis (slow)
 

vikasjn

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DC is a synthesis tool while PT is a static timing analysis tool ... what does it exactly mean ...the post above give u a genral idea ... ok it is true that DC also has a internal STA engine that is not directly controllable ... dc uses it for it's own analysis ... selfish!! ...The other thing is u genrally use PT for timing closure ... not dc ...b'cos dc for once cannot be used to check the circuit performance in different modes (i'm not talking about worst and best ... dc CAN do that .. and it does ) ...there is one more post in this forum complaining that he got a lot of modes from his asic library .. i 'm talking about those modes ... also DC is not able to read the SPEF (standard parasitic exchange format) ..files which has the parastic extracts to calcultae the exact delay on silicon .. PT is ..so to cut the long story short
DC is a synthesis tool (with a weak STA engine)
PT is a full fledge STA tool used to prove timing clouser
 

dumeHCM

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vikasjn said:
also DC is not able to read the SPEF (standard parasitic exchange format) ..files which has the parastic extracts to calcultae the exact delay on silicon ..
I wonder if you know what you are talking about. DC is a tool , in a layman language, to translate your code writen in RTL which is technology independent to a gate level with a target technoly. There is no SPEF in RTL code, after you Place and Route then we start talking about SPEF.
 

dumeHCM

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tutx said:
dumeHCM said:
Design compiler is a synthesis tool
Prime time is a verification tool (timing requirement)
Synthesis and Verification, what is the main differences between them? Sometime, I make two in one. It's really true or not ? I seem that synthesis became one part of verification (!).
The general flow is this:

From the spec -design vy RTL code-Verify by verilog(or VHDL)-simulation-Synthesized by Dc -verify by PT-Place and Route-Verified -Maybe simulated again. It's just a simple flow
 

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