Difference between dataflow and behavioral model in verilog?

[deepa1206]

Can anyone explain the difference between dataflow and behavioral model in verilog.. i have been searching the internet and havent been able to find concrete answers.

thanks

 

[Tan]

Re: Difference between dataflow and behavioral model in veri

Can anyone explain the difference between dataflow and behavioral model in verilog.. i have been searching the internet and havent been able to find concrete answers.

thanks

Hi deepa,
Its very simple.Name itself explains what they are.Dataflow is one way of describing the program.Like describing the logical funtion of a particular design.
Behavioral model on the other hand describes the behavior of the system.How does it behave when particular input is given?

I hope its clear.

 

[deepa1206]

Re: Difference between dataflow and behavioral model in veri

Thank you Tan. I was going through some examples, and I saw that only "assign" statement is primarily used in dataflow model. Does that mean that dataflow cannot be used for sequential behavior?

 

[Tan]

Re: Difference between dataflow and behavioral model in veri

In a way you can say that it cannot be sequential.Because dataflow is logical representation.You can say them as defining equations in vhdl format.so you dont require a clock.If you dont need a clock there is no point for sequential circuits.