[SOLVED] difference between current and voltage-mode circuits

[preethi19]

Hi when we take the case of a CMOS multiplier circuit we have them in both current and voltage mode... Can anyone kindly let me know how is one advantageous over the other if in the end both perform the same multiplier function. Thank you!!!

 

[dick_freebird]

What is the natural form of your operands? A voltage, or
a current? Simplicity argues for using the multiplier form
that requires the least translation (which always adds
something you don't want, and costs you something you
do).

A current mirror is simpler than a voltage buffer, and you
can do addition with current sources in parallel much
easier than addition of two voltage sources.

 

[preethi19]

I can observe from many papers that current mode is more simple than voltage mode in complexity, high frequency, high dynamic range, low power consumption. I also read it is possible to eliminate temperature variation and other technological parameters using current mode. But in the paper "Four-Quadrant CMOS analog multiplier based on new current squarer circuit with high speed" i noticed that it has temperature dependence. I can understand from that and many papers that regardless of voltage or current, your design plays a role in eliminating all these temperature and other variations. Also i am dealing with multiplier in current mode. I was able to find many papers in voltage mode with simple multiplication function independent of temperature dependence. Also they were less complex in structure. So wer is the actual difference between these two?

Current mode circuits have less loop gain. Can anyone explain what does this mean. Amplifiers have feedback and are in a loop but what about a simple analog multiplier. Where is the loop in a multiplier. I'm new and trying to learn all this. Any help would be really great!!! Thank you!!!