Hi,
Some differences i'm listing,
FPGAs,
Large no. of flipflops, i.e. sequential logic.
Volatile...need reprogramming on power up(sram based).
can have embeded processors, multipliers n on-chip rams.Also clock management is highly advanced.
for complex applications.
CPLDs,
More amount of combinatoional logic.
PAL based, Once programmed no need of reconfiguration unless design change.
Better predictable delays.
For small designs with large decoding logic and low power consumption.