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Another question: Let's say that if I want to design a adder using FPGA, we store the execution code in the FPGA, specifically in the LUT. Am I right? If I'm right, then how can FPGA keep the execution code? Because I think that LUT is a RAM, it is volatile. When it is powered off, it cannot store the execution code any more. Maybe it is not the most suitable example, but I think it can make me understand how FPGA works. Hope someone can help me out. Thanks in advance.