In fact, the subset of synthesizable Verilog/VHDL is IEEE standard or industrial standard. In most cases, don't worry about it. You could use the same code for FPGA or ASIC. However, in the real lab work, you have
- Keep in mind the device specific feathers (FPGA) and the techology specific features (ASIC), if you used the hard block or IP, most frequently memory, you have to see if they are the same.
- the tool specific feathers. You are using different tools in synthesis the code. Some tools provide the tool specific directives, if you use some of them, change your code if neccissary.
FPGA always use "one-hot" statemachine, but done worry about it. Most tools could change it automatically.
soccer,
The original poster was asking about the difference between "ASIC RTL code and FPGA RTL Code".
The answer is that with RTL code, the answer is, there isn't much difference.
That's one advantage of RTL, technology freedom, common language.
You can write "pure" RTL that is usable for both FPGA and ASIC, but if you want to take advantage of some special stuff available on FPGAs you may have to customise your code to suit the FPGA architecture of your design
lincolndsp,
FPGA imples DSP? I don't think so..
coolrak,
I'm not sure about that. I believe gated clocks can be implemented in FPGA's. In Spartan and Virtex parts at least.